Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9953993-B2
Application number	US-201715457316-A
Country	US
Kind code	B2
Filing date	Mar 13, 2017
Priority date	Jul 25, 2016
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A semiconductor memory device includes a plurality of word lines stacked in a first direction; a semiconductor pillar extending through the plurality of word lines in the first direction; a source line electrically connected to the semiconductor pillar; and a transistor arranged in the first direction with the plurality of word lines. The transistor includes a gate electrode, source and drain regions positioned on both sides of the gate electrode respectively. The source line is positioned between the transistor and the plurality of word lines, and is electrically connected to one of the source and drain regions.

First claim

What is claimed is:

1. A semiconductor memory device, the device comprising:
a plurality of word lines stacked in a first direction;
a semiconductor pillar extending through the plurality of word lines in the first direction;
a source line electrically connected to the semiconductor pillar; and
a transistor arranged in the first direction with the plurality of word lines and including a gate electrode, source and drain regions positioned on both sides of the gate electrode respectively,
the source line being positioned between the transistor and the plurality of word lines, and being electrically connected to one of the source and drain regions.

2. The device according to claim 1 , further comprising:
a first interconnect wire provided between the transistor and the source line,
the source line being electrically connected to the one of the source and drain regions via the first interconnect wire.

3. The device according to claim 2 , further comprising:
a first contact plug electrically connecting the first interconnect wire and the source line.

4. The device according to claim 1 , further comprising:
a second contact plug extending in the first direction through the source line and the plurality of word lines, and electrically connected to the other of the source and drain regions; and
a second interconnect wire electrically connected to the second contact plug,
the plurality of word lines being positioned between the second interconnect wire and the source line.

5. The device according to claim 1 , further comprising:
a third contact plug electrically connected to an end portion of the source line, and extending in the first direction,
the end portion of the source line is provided in stairs with end portions of the plurality of word lines.

6. The device according to claim 1 , further comprising:
a fourth contact plug extending in the first direction through the source line and the plurality of word lines, and electrically connected to the one of the source and drain regions;
a fifth contact plug extending in the first direction through the plurality of word lines, and electrically connected to the source line; and
a third interconnect wire electrically connecting the fourth contact plug and the fifth contact plug,
the plurality of word lines being positioned between the third interconnect wire and the source line.

7. The device according to claim 6 , wherein
the fourth contact plug is positioned between the transistor and the third interconnect wire.

8. The device according to claim 6 , wherein
the fourth contact plug and the fifth contact plug include metal.

9. The device according to claim 6 , further comprising:
a fourth interconnect wire provided between the source line and the transistor, and electrically connected to the one of the source and drain regions and to the fourth contact plug,
the fifth contact plug being positioned between the third interconnect wire and the fourth interconnect wire.

10. The device according to claim 6 , further comprising:
a bit line electrically connected to the semiconductor pillar,
the plurality of word lines being positioned between the source line and the bit line, and the third interconnect wire being included in an interconnect layer same as the bit line.

11. The device according to claim 6 , further comprising:
a sixth contact plug extending in the first direction through the source line and the plurality of word lines, and electrically connected to the other of the source and drain regions; and
a fifth interconnect wire electrically connected to the sixth contact plug,
the plurality of word lines being positioned between the fifth interconnect wire and the source line.

12. The device according to claim 11 , wherein
the fifth interconnect wire supplies a predetermined potential to the source line.

13. The device according to claim 11 , further comprising:
a seventh contact plug electrically connected to an end portion of the source line, and extending in the first direction,
the end portion of the source line is provided in stairs with end portions of the plurality of word lines.

14. The device according to claim 1 , wherein
the source line is a plate-shaped conductor crossing the first direction.

15. The device according to claim 14 , wherein
the source line includes metal or conductive polycrystalline silicon.

16. A semiconductor memory device, the device comprising:
a transistor including a control electrode and first and second semiconductor regions positioned on both sides of the control electrode;
a plurality of electrode layers stacked on the transistor;
an interconnect body provided between the transistor and the plurality of electrode layers;
a semiconductor pillar extending in a stacking direction of the plurality of electrode layers through the plurality of electrode layers, and electrically connected to the interconnect body;
a first conductive body extending in the stacking direction through the plurality of electrode layers and the interconnect body, and electrically connected to one of the first and second semiconductor regions;
a second conductive body extending in the stacking direction through the plurality of electrode layers, and electrically connected to the interconnect body; and
a first interconnect wire electrically connecting the first conductive body and the second conductive body,
the plurality of electrode layers being positioned between the interconnect body and the first interconnect wire.

17. The device according to claim 16 , wherein
the first conductive body is positioned between the transistor and the first interconnect wire.

18. The device according to claim 16 , further comprising:
a third conductive body extending in the stacking direction through the plurality of electrode layers and the interconnect body, and electrically connected to the other of the first and second semiconductor regions; and
a second interconnect wire electrically connected to the third conductive body,
the plurality of electrode layers being positioned between the interconnect body and the second interconnect wire.

19. The device according to claim 16 , further comprising:
a third interconnect wire provided between the interconnect body and the transistor, and electrically connected to the one of the first and second semiconductor regions and to the first conductive body,
the second conductive body being positioned between the first interconnect wire and the third interconnect wire.

20. The device according to claim 18 , further comprising:
a fourth conductive body electrically connected to an end portion of the interconnect body, and extending in the stacking direction,
the end portion of the interconnect body being provided in stairs with end portions of the plurality of electrode layers.

Assignees

• Toshiba Memory Corp

Inventors

• Utsumi Tetsuaki
• Isobe Katsuaki

Classifications

• H01L27/1157

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic

• H01L27/11556 Primary

  Electricity · mapped topic