Package assembly with thermal interface material gutter

Patent metadata

Field	Value
Publication number	US-12557653-B2
Application number	US-202318099949-A
Country	US
Kind code	B2
Filing date	Jan 22, 2023
Priority date	Jan 22, 2023
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A method and apparatus are provided which manages the movement of thermal interface material (TIM) squeezed out from between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes an IC die mounted on a substrate and covered by a lid. A bottom surface of the lid has a die overlapped region facing a top surface of the IC die. The bottom surface of the lid has a first gutter formed therein. An outer sidewall of the first gutter is formed outward of the first die overlapped region as to receive TIM squeezed out from between a lid and an IC die.

First claim

What is claimed is:

1 . A chip package, comprising:
a substrate; a first IC die coupled to the substrate, the first IC die having a top surface bounded by edges; and a lid having a top surface and a bottom surface, the bottom surface facing away from the top surface and towards the first IC die, the bottom surface of the lid having a first die overlapped region facing a top surface of the first IC die, the bottom surface of the lid having a first gutter formed therein, at least a portion of the first gutter aligned in a common direction with at least one of the edges of the top surface of the first IC die, and an outer sidewall of the first gutter formed outward of the first die overlapped region, the lid having a first pad extending away from the top surface of the lid, the first gutter formed in the first pad, the first pad comprising a plurality of grooves, and wherein the first gutter has a depth that is at least an order of magnitude greater than a depth of the plurality of grooves.

2 . The chip package of claim 1 , wherein the first gutter circumscribes the first die overlapped region.

3 . The chip package of claim 1 further comprising:
a second IC die coupled to the substrate next to the first IC die, the second IC die having a top surface bounded by edges, wherein the top surface of the second IC die faces a second die overlapped region defined on a bottom surface of the lid.

4 . The chip package of claim 3 , wherein the first gutter formed in the bottom surface of the lid circumscribes both the first IC die and the second IC die.

5 . The chip package of claim 3 , wherein the bottom surface of the lid further comprises:
a second pad extending away from the top surface of the lid; and a second gutter formed in the second pad, at least a portion of the second gutter aligned in a common direction with at least one of the edges of the top surface of the second IC die, and an outer sidewall of the second gutter formed outward of the second die overlapped region.

6 . The chip package of claim 3 , wherein the bottom surface of the lid further comprises:
a second gutter having at least a portion of the second gutter aligned in a common direction with at least one of the edges of the top surface of the second IC die, and an outer sidewall of the second gutter formed outward of the second die overlapped region, a portion of the first and second gutters passing between the first and second die overlapped regions.

7 . The chip package of claim 1 , wherein the first gutter circumscribes the first die overlapped region.

8 . The chip package of claim 1 , wherein the first gutter is entirely disposed outward of the first die overlapped region.

9 . The chip package of claim 1 , wherein an inner sidewall of the first gutter is formed inside the first die overlapped region.

10 . The chip package of 1 , wherein the lid further comprises:
a cavity defined in the lid configured to contain a phase change material or flow fluid therethrough.

11 . The chip package of 1 , wherein the top surface of the lid further comprises:
a plurality of heat transfer fins.

12 . A chip package, comprising:
a substrate; a first IC die coupled to the substrate, the first IC die having a top surface bounded by edges; and a lid having a top surface and a bottom surface, the bottom surface facing away from the top surface and towards the first IC die, the bottom surface of the lid having a first gutter and a plurality of grooves formed therein, the first gutter has a depth that is at least an order of magnitude greater than a depth of the plurality of grooves, an outer sidewall of the first gutter formed outward of a first die overlapped region.

13 . The chip package of 12 , wherein the lid further comprises:
a pad extending away from the top surface of the lid, the first gutter and the plurality of grooves formed in the pad, the pad disposed directly over the first IC die.

14 . The chip package of 12 , wherein the lid further comprises one or more heat transfer mechanisms selected from the group consisting of:
(a) phase change material disposed in a cavity defined in the lid; (b) a plurality of heat transfer fins; (c) thermoelectric heat pump; (d) a forced fluid heat exchanger; and (e) a heat pipe.

15 . A chip package, comprising:
a substrate; a first IC die coupled to the substrate, the first IC die having a top surface bounded by edges; and a lid having a top surface and a bottom surface, the bottom surface facing away from the top surface and towards the first IC die, the bottom surface of the lid having a first die overlapped region facing a top surface of the first IC die, the bottom surface of the lid having a first gutter formed therein, at least a portion of the first gutter aligned in a common direction with at least one of the edges of the top surface of the first IC die, and an outer sidewall of the first gutter formed outward of the first die overlapped region; and a second IC die coupled to the substrate next to the first IC die, the second IC die having a top surface bounded by edges, wherein the top surface of the second IC die faces a second die overlapped region defined on a bottom surface of the lid, wherein the bottom surface of the lid further comprises:
a second gutter having at least a portion of the second gutter aligned in a common direction with at least one of the edges of the top surface of the second IC die, and an outer sidewall of the second gutter formed outward of the second die overlapped region, a portion of the first and second gutters passing between the first and second die overlapped regions.

16 . The chip package of claim 15 , wherein the first gutter circumscribes the first die overlapped region.

17 . The chip package of claim 15 , wherein the first gutter formed in the bottom surface of the lid circumscribes both the first IC die and the second IC die.

18 . The chip package of claim 17 , wherein the bottom surface of the lid further comprises:
a first pad extending away from the top surface of the lid, the first gutter formed in the first pad.

19 . The chip package of claim 18 , wherein the bottom surface of the lid further comprises:
a second pad extending away from the top surface of the lid; and wherein the second gutter is formed in the second pad, at least a portion of the second gutter aligned in a common direction with at least one of the edges of the top surface of the second IC die, and an outer sidewall of the second gutter formed outward of the second die overlapped region.

20 . The chip package of claim 15 , wherein the first gutter circumscribes the first die overlapped region.

21 . The chip package of claim 15 , wherein the first gutter is entirely disposed outward of the first die overlapped region.

22 . The chip package of claim 15 , wherein an inner sidewall of the first gutter is formed inside the first die overlapped region.

23 . The chip package of claim 15 , the lid having a pad extending away from the top surface of the lid, the first gutter formed in the pad, the pad comprising a plurality of grooves, and wherein the first gutter has a depth that is at least an order of magnitude greater than a depth of the plurality of grooves.

Assignees

• Advanced Micro Devices Inc

Inventors

• Flynn Michael
• Joe Otto

Classifications

• H10W72/20 Primary

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W90/00

  Package configurations · CPC title