Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management

Patent metadata

Field	Value
Publication number	US-10529645-B2
Application number	US-201715617774-A
Country	US
Kind code	B2
Filing date	Jun 8, 2017
Priority date	Jun 8, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.

First claim

What is claimed is:

1. An integrated circuit (IC) package, comprising:
one or more IC dies having backside recessed areas; and
a lid including:
an outer surface;
a first inner surface; and
one or more second inner surfaces recessed from the first inner surface to form one or more indentations in the lid, wherein at least one of the indentations is configured to extend beyond a boundary surrounding lateral surfaces of the one or more IC dies, the at least one of the indentations being configured to stretch across a vertical projection of an edge of the boundary.

2. The IC package of claim 1 , wherein the one or more indentations comprise four indentations.

3. The IC package of claim 2 , wherein the four indentations are disposed in a rectangular arrangement.

4. The IC package of claim 1 , wherein each of one or more locations of the lid includes a plurality of the indentations in the lid.

5. The IC package of claim 1 , further comprising:
one or more third inner surfaces; and
one or more fourth inner surfaces, each fourth inner surface coupling one of the second inner surfaces to one of the third inner surfaces.

6. The SIC package of claim 5 , wherein at least one of the fourth inner surfaces is a chamfered surface.

7. The IC package of claim 5 , wherein at least one of the fourth inner surfaces is a curved surface.

8. The IC package of claim 5 , wherein at least one of the fourth inner surfaces has a stepped profile.

9. An integrated circuit (IC) package comprising:
a package substrate;
one or more IC dies disposed above the package substrate, the one or more IC dies having backside recessed areas;
a thermal interface material (TIM) disposed above the IC dies; and
a lid disposed above the TIM and comprising:
an outer surface;
a first inner surface; and
one or more second inner surfaces recessed from the first inner surface to form one or more indentations in the lid, wherein the one or more indentations are configured to extend beyond a boundary surrounding lateral surfaces of the one or more IC dies and wherein at least one of the indentations is configured to stretch across a vertical projection of an edge of the boundary.

10. The IC package of claim 9 , wherein the TIM is thicker in areas underneath the one or more indentations than in a region between the one or more IC dies and the first inner surface of the lid.

11. The IC package of claim 9 , wherein the one or more indentations are configured to receive a portion of the TIM that is forced out from between one or more upper surfaces of the one or more IC dies and the first inner surface of the lid.

12. The IC package of claim 9 , wherein the one or more indentations are located above one or more corners of the one or more IC dies.

13. The IC package of claim 9 , wherein the lid further comprises:
one or more third inner surfaces; and
one or more fourth inner surfaces, each fourth inner surface coupling one of the second inner surfaces to one of the third inner surfaces.

14. The IC package of claim 13 , wherein at least one of the fourth inner surfaces is a chamfered surface.

15. The IC package of claim 13 , wherein at least one of the fourth inner surfaces is a curved surface.

16. The IC package of claim 9 , further comprising a heat sink assembly disposed above the lid.

17. The IC package of claim 9 , wherein the at least one of the indentations is configured to stretch across the vertical projection of the edge of the boundary such that the at least one of the indentations is disposed both above a first area disposed inside the boundary and above a second area disposed outside the boundary.

18. The IC package of claim 9 , wherein the one or more indentations are located only in one or more corners of the boundary surrounding the lateral surfaces of the one or more IC dies.

19. The IC package of claim 18 , wherein the boundary is rectangular and wherein the one or more indentations comprise one indentation located in each of the four corners of the rectangular boundary.

20. The IC package of claim 9 , wherein the TIM is disposed in the at least one of the indentations configured to stretch across the vertical projection of the edge of the boundary.

Assignees

• Xilinx Inc

Inventors

• Gandhi Jaspreet Singh
• Liu Henley
• Lee Tien-Yu
• Refai-Ahmed Gamal
• Kim Myongseob
• Fernandez Ferdinand F
• Barber Ivor G
• Ramalingam Suresh

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W76/63

  characterised by their shape or disposition, e.g. between cap and walls of a container · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title