Method of forming a gap under a source/drain feature of a multi-gate device

Patent metadata

Field	Value
Publication number	US-12538532-B2
Application number	US-202217848701-A
Country	US
Kind code	B2
Filing date	Jun 24, 2022
Priority date	May 9, 2022
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

Multi-gate transistor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a fin-shaped structure over a substrate and including channel layers interleaved by sacrificial layers, recessing the fin-shaped structure to form a source/drain recess, recessing the sidewalls of the sacrificial layers to form inner spacer recesses, depositing a dielectric layer over the substrate and the inner spacer recesses, depositing a polymer layer over the dielectric layer, etching back the polymer layer and the dielectric layer to form inner spacer features in the inner spacer recesses and an inner spacer layer over the portion of the substrate, and epitaxially depositing more than one epitaxial layer from the sidewalls of the plurality of channel layers to form a source/drain feature in the source/drain recess. The source/drain feature and the inner spacer layer define a gap.

First claim

What is claimed is:

1 . A method, comprising:
forming a fin-shaped structure over a substrate, the fin-shaped structure comprising a plurality of channel layers interleaved by a plurality of sacrificial layers; recessing a source/drain region of the fin-shaped structure to form a source/drain recess that exposes a portion of the substrate, sidewalls of the plurality of sacrificial layers, and sidewalls of the plurality of channel layers; selectively and partially recessing the sidewalls of the plurality of sacrificial layers to form inner spacer recesses; conformally depositing a dielectric layer over the substrate and the inner spacer recesses; depositing a polymer layer over the dielectric layer; after the depositing of the polymer layer, curing the polymer layer such that a topmost surface of the cured polymer layer is lower than a top surface of a topmost one of the plurality of channel layers; after the curing, etching back the polymer layer and the dielectric layer to form inner spacer features in the inner spacer recesses and an inner spacer layer over the portion of the substrate; and epitaxially depositing more than one epitaxial layer from the sidewalls of the plurality of channel layers to form a source/drain feature in the source/drain recess, wherein the source/drain feature and the inner spacer layer define a gap.

2 . The method of claim 1 , wherein the dielectric layer comprises silicon, oxygen, carbon, and nitrogen.

3 . The method of claim 1 , wherein the polymer layer comprises fluorinated silicone or fluorinated polysilane.

4 . The method of claim 1 , wherein the depositing of the polymer layer comprises chemical vapor deposition (CVD), spin-on coating, or flowable CVD (FCVD).

5 . The method of claim 1 , wherein surfaces of the inner spacer layer are substantially free of the more than one epitaxial layer.

6 . The method of claim 1 , wherein, during the etching back, an etching rate of the polymer layer is smaller than an etching rate of the dielectric layer.

7 . The method of claim 1 , further comprising:
after the etching back, selectively removing the polymer layer.

8 . The method of claim 1 , wherein, after the etching back, the substrate is substantially covered by the inner spacer layer.

9 . A method, comprising:
receiving a workpiece comprising:
a substrate, and
a fin-shaped structure over the substrate, the fin-shaped structure comprising a base fin and a semiconductor stack over the base fin, the semiconductor stack comprising first semiconductor layers interleaved by second semiconductor layers;
forming a dummy gate stack over a channel region of the fin-shaped structure; depositing a top spacer layer over the workpiece; after the depositing of the top spacer layer, recessing the workpiece to form a source/drain recess over a source/drain region of the fin-shaped structure, the source/drain recess extending into the substrate and exposing sidewalls of the first semiconductor layers and the second semiconductor layers; selectively and partially recessing the sidewalls of the second semiconductor layers to form inner spacer recesses; conformally depositing a dielectric layer over the substrate and the inner spacer recesses; depositing a polymer layer over the dielectric layer; after the depositing of the polymer layer, curing the polymer layer such that a topmost surface of the cured polymer layer is lower than a top surface of a topmost one of the first semiconductor layers; after the curing, etching back the polymer layer and the dielectric layer to form inner spacer features in the inner spacer recesses and an inner spacer layer over the substrate; after the etching back, removing the polymer layer; selectively depositing a first epitaxial layer on the sidewalls of the first semiconductor layers; and selectively depositing a second epitaxial layer on surfaces of the first epitaxial layer, wherein the inner spacer layer comprises a bottom portion disposed on a top facing portion the substrate and a sidewall portion disposed on a sidewall of the substrate, wherein a thickness of the bottom portion is greater than a thickness of the sidewall portion.

10 . The method of claim 9 ,
wherein the first epitaxial layer and the second epitaxial layer comprise a semiconductor material and a dopant, wherein a first concentration of the dopant in the first epitaxial layer is smaller than a second concentration of the dopant in the second epitaxial layer.

11 . The method of claim 9 , wherein a bottom surface of the second epitaxial layer is lower than a top surface of the base fin by between about 1 nm and about 15 nm.

12 . The method of claim 9 , wherein a bottom surface of the second epitaxial layer is higher than a top surface of the base fin by between about 1 nm and about 5 nm.

13 . The method of claim 9 , wherein a top surface of the bottom portion is spaced apart from the second epitaxial layer by a gap.

14 . The method of claim 13 , wherein the depositing of the top spacer layer forms a first spacer sidewall and a second spacer sidewall extending along sidewalls of the base fin.

15 . The method of claim 14 , wherein the gap is disposed between the first spacer sidewall and the second spacer sidewall.

16 . A method, comprising:
forming a fin-shaped structure over a substrate, the fin-shaped structure comprising a base fin rising from the substrate and a semiconductor stack over the base fin, the semiconductor stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers; forming a dummy gate stack over a channel region of the fin-shaped structure; recessing a source/drain region of the fin-shaped structure to form a source/drain recess extending into the base fin; selectively and partially recessing the sacrificial layers over the channel region to form inner spacer recesses; conformally depositing a dielectric layer over the inner spacer recesses and the source/drain recess; depositing a polymer layer over the dielectric layer; after the depositing, curing the polymer layer such that a topmost surface of the cured polymer layer is lower than a top surface of a topmost one of the plurality of channel layers but is higher than a second topmost one of the plurality of channel layers; after the curing, etching back the cured polymer layer and the dielectric layer to form inner spacer features in the inner spacer recesses and a bottom spacer layer over the source/drain recess; after the etching back, removing the polymer layer; selectively depositing a first epitaxial layer on sidewalls of the plurality of channel layers; selectively depositing a second epitaxial layer on surfaces of the first epitaxial layer; and depositing a third epitaxial layer over the second epitaxial layer, wherein the polymer layer comprises fluorinated silicone or fluorinated polysilane.

17 . The method of claim 16 , wherein the depositing of the polymer layer comprises depositing the polymer layer using chemical vapor deposition (CVD), flowable CVD, or spin-on coating.

18 . The method of claim 16 , wherein the curing comprises annealing or use of ultraviolet (UV) radiation.

19 . The method of claim 16 , wherein a top surface of the bottom spacer layer is spaced apart from the second epitaxial layer by a gap.

20 . The method of claim 16 , wherein the dielectric layer comprises silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, or carbon-rich silicon carbonitride.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che-Lun
• Lee Wei-Yang
• Lin Chia-Pin

Classifications

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D84/0128

  Manufacturing their channels · CPC title