Horizontal gate-all-around device having wrapped-around source and drain

Patent metadata

Field	Value
Publication number	US-9754840-B2
Application number	US-201514942696-A
Country	US
Kind code	B2
Filing date	Nov 16, 2015
Priority date	Nov 16, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A method of forming a semiconductor device includes forming a fin extending from a substrate. The fin has a source/drain (S/D) region and a channel region. The fin includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer has a first composition, and the second semiconductor layer has a second composition different from the first composition. The method further includes removing the first semiconductor layer from the S/D region of the fin such that a first portion of the second semiconductor layer in the S/D region is suspended in a space. The method further includes epitaxially growing a third semiconductor layer in the S/D region, the third semiconductor layer wrapping around the first portion of the second semiconductor layer.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a fin extending from a substrate, the fin having a source/drain (S/D) region and a channel region, wherein the fin includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, the first semiconductor layer has a first composition, and the second semiconductor layer has a second composition different from the first composition;
removing the first semiconductor layer from the S/D region of the fin such that a first portion of the second semiconductor layer in the S/D region is suspended in a space; and
epitaxially growing a third semiconductor layer in the S/D region, the third semiconductor layer wrapping around the first portion of the second semiconductor layer, and the third semiconductor layer having a portion disposed between a remaining portion of the first semiconductor layer and the first portion of the second semiconductor layer.

2. The method of claim 1 , wherein the third semiconductor layer is doped with a higher dopant concentration than the second semiconductor layer.

3. The method of claim 2 , wherein the second and the third semiconductor layers each include silicon.

4. The method of claim 1 , further comprising:
removing the first semiconductor layer from the channel region of the fin such that a second portion of the second semiconductor layer is suspended in a space; and
forming a gate stack over the channel region of the fin, wherein a portion of the gate stack wraps around the second portion of the second semiconductor layer.

5. The method of claim 4 , wherein the first and second portions of the second semiconductor layer have different cross-sectional profiles.

6. The method of claim 1 , further comprising, before the removing of the first semiconductor layer from the S/D region of the fin:
forming a dummy gate stack covering the channel region of the fin.

7. The method of claim 6 , further comprising, after the epitaxially growing of the third semiconductor layer:
forming an inter-layer dielectric (ILD) layer over the third semiconductor layer;
removing the dummy gate stack to expose the channel region of the fin;
removing the first semiconductor layer from the channel region of the fin such that a second portion of the second semiconductor layer is suspended in a space; and
forming a gate stack over the channel region of the fin, wherein a portion of the gate stack wraps around the second portion of the second semiconductor layer.

8. The method of claim 1 , wherein the first semiconductor layer includes silicon germanium and the second semiconductor layer includes silicon.

9. The method of claim 1 , wherein the first portion of the second semiconductor layer and the third semiconductor layer collectively form a vertical bar-like shape.

10. A method of forming a semiconductor device, the method comprising:
forming a fin extending from a substrate, the fin having a plurality of first semiconductor layers and a plurality of second semiconductor layers, the first and second semiconductor layers being alternately stacked;
forming a dummy gate stack over a channel region of the fin;
removing portions of the first semiconductor layers from S/D regions of the fin such that first portions of the second semiconductor layers in the S/D regions each are suspended in a respective space;
epitaxially growing a third semiconductor layer in the S/D regions, wherein the third semiconductor layer wraps around each of the first portions of the second semiconductor layers;
removing the dummy gate stack, thereby exposing the channel region of the fin;
removing portions of the first semiconductor layers from the channel region of the fin such that second portions of the second semiconductor layers in the channel region each are suspended in a respective space; and
forming a gate stack over the channel region of the fin, wherein the gate stack wraps around each of the second portions of the second semiconductor layers.

11. The method of claim 10 , further comprising, before the removing of the dummy gate stack:
forming an inter-layer dielectric (ILD) layer over the third semiconductor layer.

12. The method of claim 10 , wherein the first semiconductor layers each include silicon germanium and the second semiconductor layers each include silicon.

13. The method of claim 10 , further comprising, before the removing of the portions of the first semiconductor layers from the S/D regions of the fin:
forming a gate spacer on sidewalls of the dummy gate stack.

14. The method of claim 10 , wherein the third semiconductor layer has a higher dopant concentration than each of the first portions of the second semiconductor layers.

15. The method of claim 10 , wherein the removing of the portions of the first semiconductor layers from the S/D regions of the fin includes an etching process tuned to selectively remove the portions of the first semiconductor layers while the first portions of the second semiconductor layers in the S/D regions remain substantially unchanged.

16. A method of forming a semiconductor device, the method comprising:
forming a fin over a substrate, the fin having a first semiconductor layer and a second semiconductor layer over the first semiconductor layer, the first and second semiconductor layers have different material compositions;
forming a first gate stack over a channel region of the fin;
removing a portion of the first semiconductor layer from a source/drain (S/D) region of the fin such that a first portion of the second semiconductor layer in the S/D region of the fin is suspended in a space;
epitaxially growing a third semiconductor layer in the S/D region of the fin, wherein the third semiconductor layer wraps around the first portion of the second semiconductor layer, and further wherein the third semiconductor layer has a portion disposed between a remaining portion of the first semiconductor layer and the first portion of the second semiconductor layer;
removing the first gate stack, thereby exposing the channel region of the fin;
removing another portion of the first semiconductor layer from the channel region of the fin such that a second portion of the second semiconductor layer in the channel region of the fin is suspended in another space; and
forming a second gate stack over the channel region of the fin, wherein the second gate stack wraps around the second portion of the second semiconductor layer.

17. The method of claim 16 , wherein the first semiconductor layer includes a first semiconductor material and is substantially dopant-free, and the third semiconductor layer includes the first semiconductor material and is doped with one of: an n-type dopant and a p-type dopant.

18. The method of claim 16 , wherein the first and third semiconductor layers are doped with a same type of dopant, and the third semiconductor layer has a higher dopant concentration than the first semiconductor layer.

19. The method of claim 18 , wherein the first and third semiconductor layers are doped with different dopant species.

20. The method of claim 16 , wherein the first and third semiconductor layers form a vertical bar-like shape in the S/D region of the fin.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chun-Hsiung
• Wu Chung-Cheng
• Diaz Carlos H
• Wang Chih-Hao
• Hsieh Wen-Hsing
• Sheu Yi-Ming

Classifications

• H01L21/823431

  Electricity · mapped topic

• H01L27/1211

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic