Integrated circuits having cross-couple constructs and semiconductor devices including integrated circuits

Patent metadata

Field	Value
Publication number	US-12532545-B2
Application number	US-202418596731-A
Country	US
Kind code	B2
Filing date	Mar 6, 2024
Priority date	Dec 22, 2017
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a first active region and a second active region, each extending on a substrate in a first horizontal direction, wherein the first active region and the second active region are in parallel to each other and have conductivity types different from each other; a first gate line that extends in a second horizontal direction that crosses the first horizontal direction, wherein the first gate line forms a first transistor with the first active region, and wherein the first transistor comprises a first gate configured to receive a first input signal; a second gate line that extends in the second horizontal direction and that forms a second transistor with the second active region, the second transistor comprising a second gate configured to receive a second input signal different from the first input signal; a third gate line that extends in the second horizontal direction between the first and second gate lines, the third gate line comprising a first partial gate line and a second partial gate line, wherein the first partial gate line forms a third transistor with the first active region, wherein the second partial gate line forms a fourth transistor with the second active region, wherein the third transistor comprises a third gate configured to receive the second input signal, and wherein the fourth transistor comprises a fourth gate configured to receive the first input signal; a first source/drain contact extending in the second horizontal direction and having a bottom surface connected to drain regions of the first and third transistors; and a second source/drain contact extending in the second horizontal direction and having a bottom surface connected to drain regions of the second and fourth transistors, wherein the first and second source/drain contacts are electrically connected to each other on a region between the first and second active regions.

2 . The integrated circuit of claim 1 , further comprising:
a first metal line, a second metal line, and a third metal line, each extending on the first and second gate lines in the first horizontal direction, the first, second, and third metal lines extending in parallel to one another, wherein the first metal line is electrically connected to the first gate line and the second partial gate line, wherein the second metal line is electrically connected to the first and second source/drain contacts, and wherein the third metal line is electrically connected to the second gate line and the first partial gate line.

3 . The integrated circuit of claim 2 , wherein the first, second, and third metal lines are arranged on the region between the first and second active regions.

4 . The integrated circuit of claim 1 , further comprising:
a first jumper electrically interconnecting source/drain regions arranged on the second active region at first and second opposite sides of the first gate line.

5 . The integrated circuit of claim 4 , wherein the first gate line continually extends in the second horizontal direction from the first active region to the second active region, and
wherein the first jumper comprises a metal pattern that is spaced apart from the first gate line and that extends in the first horizontal direction.

6 . The integrated circuit of claim 1 , wherein the first gate line comprises a third partial gate line overlapping the first active region in a direction perpendicular to the first horizontal direction and the second horizontal direction, the third partial gate line having an end on the region between the first and second active regions.

7 . The integrated circuit of claim 6 , wherein a portion of the second active region is free from overlap by a portion of the first gate line in the direction perpendicular to the first horizontal direction and the second horizontal direction.

8 . The integrated circuit of claim 6 , wherein the second gate line comprises a fourth partial gate line that overlaps the second active region in the direction perpendicular to the first horizontal direction and the second horizontal direction, the fourth partial gate line having an end on the region between the first and second active regions.

9 . An integrated circuit comprising:
a first active region and a second active region, each extending in a first horizontal direction; a first gate line extending over the first active region in a second horizontal direction that crosses the first horizontal direction; a second gate line extending over the second active region in the second horizontal direction; a first partial gate line extending over the first active region in the second horizontal direction and between the first gate line and the second gate line in the first horizontal direction, the first partial gate line configured to receive a second input signal; a second partial gate line extending over the second active region in the second horizontal direction and between the first gate line and the second gate line in the first horizontal direction, the second partial gate line configured to receive a first input signal different from the second input signal; a first source/drain contact extending in the second horizontal direction between the first gate line and the first partial gate line; a second source/drain contact extending in the second horizontal direction between the second gate line and the second partial gate line; a first jumper electrically interconnecting source/drain regions on the second active region; and a second jumper electrically interconnecting source/drain regions on the first active region, wherein the first source/drain contact and the second source/drain contact overlap in the first horizontal direction between the first active region and the second active region, wherein the first partial gate line and the second partial gate line are separated from each other between the first active region and the second active region, and wherein the first partial gate line and the second partial gate line are aligned in the second horizontal direction.

10 . The integrated circuit of claim 9 , further comprising a first metal line extending in the first horizontal direction,
wherein the first metal line is electrically connected to the first source/drain contact and to the second source/drain contact, and wherein the first partial gate line and the second partial gate line are electrically separated from each other between the first active region and the second active region.

11 . The integrated circuit of claim 10 , further comprising a second metal line and a third metal line, each extending in the first horizontal direction,
wherein the second metal line is electrically connected to the second gate line and to the first partial gate line, and wherein the third metal line is electrically connected to the first gate line and to the second partial gate line.

12 . The integrated circuit of claim 11 , wherein the first metal line, the second metal line and the third metal line extend in the first horizontal direction over a region between the first active region and the second active region.

13 . The integrated circuit of claim 9 , wherein the first gate line overlaps the first jumper in a vertical direction and is insulated from the first jumper, and
wherein the second gate line overlaps the second jumper in the vertical direction and is insulated from the second jumper.

14 . The integrated circuit of claim 9 , wherein each of the first jumper and the second jumper comprises a respective upper contact extending in the first horizontal direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Do Jung-Ho
• Lee Dal-Hee
• Lim Jin-Young
• Song Tae-Joong
• Jung Jong-Hoon

Classifications

• G11C11/412

  using field-effect transistors only · CPC title

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10D84/975

  Wiring regions or routing · CPC title

• H10D84/907

  CMOS gate arrays · CPC title