Integrated circuit, semiconductor device based on integrated circuit, and standard cell library

Patent metadata

Field	Value
Publication number	US-9431383-B2
Application number	US-201514801121-A
Country	US
Kind code	B2
Filing date	Jul 16, 2015
Priority date	Jul 22, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising:
at least one cell including,
a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction, the second direction being perpendicular to the first direction;
first contacts including a first left contact between a first conductive line and a second conductive line of the plurality of conductive lines; and
a second contact on the second conductive line and the first contacts, the second contact electrically connected to the second conductive line and the first contacts and electrically isolated from the first conductive line such that the second contact, the second conductive line, and the first contacts form a single node.

2. The IC of claim 1 , wherein the first contacts extend in the first direction and the second contact extends in the second direction.

3. The IC of claim 1 , wherein the second contact extends in a direction perpendicular to the first contacts.

4. The IC of claim 1 , wherein each of the at least one cell further comprises:
first and second active regions having different conductive types, and wherein,
the second contact is on at least a selected one of the first and second active regions.

5. The IC of claim 4 , wherein
the plurality of conductive lines respectively correspond to a plurality of gate electrodes, and
a number of first transistors in the first active region is less than a number of second transistors in the second active region.

6. The IC of claim 4 , wherein
the plurality of conductive lines respectively correspond to a plurality of gate electrodes, and
a number of first transistors in the first active region is equal to or greater than a number of second transistors in the second active region.

7. The IC of claim 4 , wherein each of the at least one cell further comprises:
a plurality of fins that extend in the second direction in the first and second active regions, the plurality of fins being in parallel to each other in the first direction.

8. The IC of claim 7 , wherein
the plurality of conductive lines respectively correspond to a plurality of gate electrodes,
the plurality of fins respectfully correspond to a plurality of fin transistors, and
a first number of the plurality of fin transistors in the first active region is less than a second number of the plurality of fin transistors in the second active region.

9. The IC of claim 7 , wherein
the plurality of conductive lines respectively correspond to a plurality of gate electrodes,
the plurality of fins respectfully correspond to a plurality of fm transistors, and
a first number of the plurality of fin transistors in the first active region is equal to or greater than a second number of the plurality of fin transistors in the second active region.

10. The IC of claim 4 , further comprising:
a cutting region between the first and second active regions, the cutting region configured to insulate the first conductive line from the single node in the second active region.

11. The IC of claim 1 , wherein
the first contacts includes the first left contact and a first right contact, the first left contact at a second side of the first conductive line, and the first right contact at a second side of the second conductive line.

12. The IC of claim 11 , wherein the second contact is on and electrically connected to the first left contact, the first right contact, and the second conductive line and a third conductive line of the plurality of conductive lines.

13. The IC of claim 11 , wherein the first contacts further comprise:
a first central contact between the second conductive line and the third conductive line.

14. The IC of claim 13 , wherein the second contact is on and electrically connected to the first left contact, the first right contact, the first central contact, the second conductive line, and the third conductive line.

15. The IC of claim 1 , wherein
the plurality of conductive lines include the first conductive line, the second conductive line and a third conductive line adjacent to each other,
the first contacts include the first left contact and a first right contact, the first left contact is between the first conductive line and the second conductive line, and the first right contact is between the second conductive line and the third conductive line, and
a length of the second contact in the second direction is greater than a distance between the first left contact and the first right contact and less than a distance between the first conductive line and the third conductive line.

16. The IC of claim 1 , wherein respective lengths of the first contacts in the second direction are smaller than a space between two adjacent conductive lines from among the plurality of conductive lines.

17. The IC of claim 1 , wherein
the first contacts have the same length in the first direction, and
the first contacts and the second contact form an H-shaped jumper.

18. The IC of claim 1 , wherein
the first contacts have different lengths in the first direction, and
the first contacts and the second contact form an L-shaped jumper.

19. A semiconductor device comprising:
a substrate including at least a first active region having a first conductive type;
a plurality of gate electrodes extending in a first direction such that the plurality of gate electrodes are parallel to each other in a second direction, the second direction being perpendicular to the first direction, the plurality of gate electrodes including at least a first gate electrode and a skipped gate electrode;
first contacts at a respective one of two sides of the skipped gate electrode of the plurality of gate electrodes, the skipped gate electrode being one of the plurality of gate electrodes connected to the first contacts; and
a second contact electrically connected to the skipped gate electrode and the first contacts in the first active region and electrically disconnected from the first gate electrode such that the second contact, the skipped gate electrode and the first contacts form a single node in the first active region.

20. The semiconductor device of claim 19 , wherein the semiconductor device includes at least one asymmetrical gated integrated circuit (IC), the asymmetrical gated IC including a greater number of transistors in a second active region than in the first active region, the second active region having a second conductive type different from the first conductive type.

21. An integrated circuit (IC) comprising:
at least one cell including,
a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction, the second direction being perpendicular to the first direction;
first contacts at a respective one of two sides of at least one conductive line from among the plurality of conductive lines; and
a second contact on the at least one conductive line and the first contacts, the second contact electrically connected to the at least one conductive line and the first contacts such that the second contact, the at least one conductive line, and the first contacts form a single node, wherein
the first contacts have one of (i) a same length in the first direction such that the first contacts and the second contact form an H-shaped jumper and (ii) different lengths in the first direction such that the first contacts and the second contact form an L-shaped jumper.

Assignees

• Baek Sang-Hoon
• Oh Sang-Kyu
• Do Jung-Ho
• Park Sun-Young
• Lee Seung-Young
• Won Hyo-Sig
• Samsung Electronics Co Ltd

Inventors

• Baek Sang-Hoon
• Oh Sang-Kyu
• Do Jung-Ho
• Park Sun-Young
• Lee Seung-Young
• Won Hyo-Sig

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10D84/975

  Wiring regions or routing · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D84/853

  comprising FinFETs · CPC title