System and method of processing cutting layout and example switching circuit

Patent metadata

Field	Value
Publication number	US-9431381-B2
Application number	US-201414500528-A
Country	US
Kind code	B2
Filing date	Sep 29, 2014
Priority date	Sep 29, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A method of processing a gate electrode cutting (CUT) layout usable for fabricating an integrated circuit (IC) is disclosed. The method includes determining if a first CUT layout pattern and a second CUT layout pattern are in compliance with a predetermined spatial resolution requirement. If the first CUT layout pattern and the second CUT layout pattern are not in compliance with the predetermined spatial resolution requirement, a merged CUT layout pattern is generated based on the first CUT layout pattern, the second CUT layout pattern, and a stitching layout pattern, and a remedial connecting layout pattern is added to a conductive layer layout. The stitching layout pattern corresponds to a carved-out portion of a third gate electrode structure. The remedial connecting layout pattern corresponds to fabricating a conductive feature electrically connecting two portions of the third gate electrode structure that are separated by the corresponding carved-out portion.

First claim

What is claimed is:

1. A method of processing a gate electrode cutting (CUT) layout usable for fabricating an integrated circuit (IC), comprising:
determining if a first CUT layout pattern and a second CUT layout pattern of the CUT layout are in compliance with a predetermined spatial resolution requirement, the first CUT layout pattern corresponding to a carved-out portion of a first gate electrode structure, and the second CUT layout pattern corresponding to a carved-out portion of a second gate electrode structure; and
if the first CUT layout pattern and the second CUT layout pattern are not in compliance with the predetermined spatial resolution requirement, then:
generating a merged CUT layout pattern based on the first CUT layout pattern, the second CUT layout pattern, and a stitching layout pattern to replace the first CUT layout pattern and the second CUT layout pattern in the CUT layout, the stitching layout pattern corresponding to a carved-out portion of a third gate electrode structure; and
adding a remedial connecting layout pattern to a conductive layer layout usable for fabricating the IC, the remedial connecting layout pattern corresponding to fabricating a conductive feature electrically connecting two portions of the third gate electrode structure that are separated by the carved-out portion of the third gate electrode structure, wherein at least one of the above operations is performed using an integrated circuit designing system comprising a processor.

2. The method of claim 1 , wherein the determining operation, the generating operation, and the adding operation are repetitively performed on all CUT layout patterns of the CUT layout.

3. The method of claim 1 , wherein
the predetermined spatial resolution requirement comprises a predetermined threshold distance; and
the determining if the first CUT layout pattern and the second CUT layout pattern are in compliance with the predetermined spatial resolution requirement comprises determining that the first CUT layout pattern and the second CUT layout pattern are not in compliance with the predetermined spatial resolution requirement if a distance between the first CUT layout pattern and the second CUT layout pattern is less than the predetermined threshold distance.

4. The method of claim 1 , wherein the stitching layout pattern has an I shape, an L shape, a Z shape, a slanted I shape, or a J shape.

5. The method of claim 1 , wherein the adding the remedial connecting layout pattern in the conductive layer layout comprises:
generating a remedial connecting layout pattern configured to overlap regions corresponding to the two portions of the third gate electrode structure that are separated by the carved-out portion of the third gate electrode structure.

6. The method of claim 1 , wherein the adding the remedial connecting layout pattern in the conductive layer layout comprises:
generating a tentative remedial connecting layout pattern configured to overlap regions corresponding to the two portions of the third gate electrode structure that are separated by the carved-out portion of the third gate electrode structure;
determining if a conductive layout pattern of the conductive layer layout and the tentative remedial connecting layout pattern are in compliance with another predetermined spatial resolution requirement, wherein the conducive layout pattern corresponds to fabricating another conductive feature;
if the conductive layout pattern and the tentative remedial connecting layout pattern are not in compliance with the another predetermined spatial resolution requirement, and if electrically connecting the another conductive feature and the conductive feature is consistent with a circuit schematic of the IC, then merging the conductive layout pattern and the tentative remedial connecting layout pattern to become the remedial connecting layout pattern in place of the conductive layout pattern; and
if the conductive layout pattern and the tentative remedial connecting layout pattern are not in compliance with the another predetermined spatial resolution requirement, and if electrically connecting the another conductive feature and the conductive feature is not consistent with the circuit schematic of the IC, then adjusting the conductive layout pattern or the tentative remedial connecting layout pattern to be further away from each other and generating the remedial connecting layout pattern based on the tentative remedial connecting layout pattern after the adjusting operation.

7. The method of claim 6 , wherein the adjusting the conductive layout pattern or the tentative remedial connecting layout pattern to be further away from each other comprises:
adjusting a shape of the merged CUT layout pattern to be further away from a region corresponding to the conductive layout pattern; and
adjusting a shape of the tentative remedial connecting layout pattern to be further away from the conductive layout pattern.

8. The method of claim 6 , wherein the adjusting the conductive layout pattern or the tentative remedial connecting layout pattern to be further away from each other comprises:
adjusting a position of the conductive layout pattern to be further away from the tentative remedial connecting layout pattern.

9. The method of claim 1 , wherein the first, second, and third gate electrode structures have a spatial resolution finer than the predetermined spatial resolution requirement of the CUT layout.

10. A method of processing a gate electrode cutting (CUT) layout usable for fabricating an integrated circuit (IC), comprising:
receiving a layout including a gate electrode layout and a CUT layout, wherein the CUT layout includes a first CUT layout pattern and a second CUT layout pattern, and a space between the first CUT layout pattern and the second CUT layout pattern is less than a predetermined spatial resolution requirement;
introducing a stitching layout pattern into the CUT layout, wherein the stitching layout connects the first CUT layout pattern and the second CUT layout pattern;
merging the first CUT layout pattern, the second CUT layout pattern, and the stitching layout pattern; and
adding a remedial connecting layout pattern to a first conductive layer of the gate electrode layout based on the stitching layout pattern, wherein at least one of the above operations is performed using an integrated circuit designing system comprising a processor.

11. The method of claim 10 , further comprises generating a non-compliance notification if the remedial connecting layout pattern is not in compliance with another predetermined spatial resolution requirement of the first conductive layer.

12. The method of claim 10 , wherein at least one of the receiving, the introducing, or the merging are repetitively performed in an iterative manner until a CUT layout is in compliance with the predetermined spatial resolution requirement.

13. The method of claim 10 , wherein adding the remedial connecting layout pattern to the first conductive layer of the gate electrode layout comprises:
determining if a conductive layout pattern of the first conductive layer layout and the remedial connecting layout pattern are in compliance with another predetermined spatial resolution requirement, wherein the conducive layout pattern corresponds to a fabrication of a conductive feature;
merging the conductive layout pattern and the remedial connecting layout pattern if the conductive layout pattern and the remedial connecting layout pattern are not in compliance with the another predetermined spatial resolution requirement; and
adjusting the conductive layout pattern or the remedial connecting layout pa

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsieh Tung-Heng
• Zhuang hui-zhong
• Lin Chung-Te
• Wang Sheng-Hsiung
• Chiang Ting-Wei
• Tien Li-Chun

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• G06F17/5072

  Physics · mapped topic