Semiconductor devices

Patent metadata

Field	Value
Publication number	US-9472659-B2
Application number	US-201514813848-A
Country	US
Kind code	B2
Filing date	Jul 30, 2015
Priority date	Nov 19, 2014
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate;
a first gate electrode on the channel layer;
a first source region of a first conductivity type at a first side of the first gate electrode; and
a first drain region of the first conductivity type at a second side of the first gate electrode,
wherein the substrate includes,
a first body region of a second conductivity type under the first source region, the first body region contacting a bottom surface and at least one sidewall of the first source region, and
a first drift region of the first conductivity type under the first drain region, the first drift region contacting a bottom surface and at least one sidewall of the first drain region, and

the semiconductor device further includes a first stud region in the channel layer and the first drift region, the first stud region having an impurity concentration higher than an impurity concentration of the first drift region.

2. The semiconductor device of claim 1 , wherein a depth of the first stud region is smaller than a depth extending from a top surface of the channel layer to a bottom surface of the first drift region.

3. The semiconductor device of claim 1 , wherein the first stud region and the first drain region are spaced apart from each other and do not overlap with each other.

4. The semiconductor device of claim 1 , further comprising:
an isolation region in the first drift region,
wherein the isolation region overlaps with a portion of the first gate electrode.

5. The semiconductor device of claim 4 , wherein a depth of the first stud region is smaller than a depth of the isolation region.

6. The semiconductor device of claim 1 , wherein the first gate electrode includes an opening, and
the first stud region is in the channel layer and the first drift region so as to correspond to the opening.

7. The semiconductor device of claim 6 , wherein the first gate electrode extends around a periphery of the opening.

8. The semiconductor device of claim 1 , wherein the first gate electrode covers the first stud region.

9. The semiconductor device of claim 1 , wherein the substrate further includes a first region and a second region,
the channel layer and the first gate electrode are in the first region, and
the semiconductor device further includes,
a second gate electrode in the second region on the substrate,
a second source region of the second conductivity type at a first side of the second gate electrode,
a second body region of the first conductivity type under the second source region, the second body region contacting a bottom surface and at least one sidewall of the second source region,
a second drain region of the second conductivity type at a second side of the second gate electrode, and
a second drift region of the second conductivity type under the second drain region, the second drift region contacting a bottom surface and at least one sidewall of the second drain region.

10. The semiconductor device of claim 9 , further comprising:
a second stud region in the second drift region,
the second stud region having an impurity concentration higher than an impurity concentration of the second drift region.

11. The semiconductor device of claim 10 , wherein the impurity concentration of the first stud region, an impurity concentration of the first source region and the impurity concentration of the first drain region, are substantially equal.

12. The semiconductor device of claim 1 , wherein the first stud region is electrically floating.

13. The semiconductor device of claim 1 , wherein the substrate includes silicon, and the channel layer includes silicon germanium.

14. The semiconductor device of claim 1 , wherein the substrate includes at least one fin type active pattern, and
the first gate electrode extends across the at least one fin type active pattern.

15. A semiconductor device, comprising:
an isolation region in a substrate;
a first active region and a second active region in a first direction with the isolation region interposed therebetween;
a first gate line extending in a second direction different from the first direction, the first gate line extending across the first active region;
a second gate line electrically connected to the first gate line, the second gate line extending in the second direction so as to be parallel with the first gate line and across the first active region, and the second gate line having a portion overlapping with the isolation region;
a source region of a first conductivity type in the first active region at a first side of the first gate line;
a drain region of the first conductivity type in the second active region,
wherein the substrate includes,
a body region of a second conductivity type under the source region, the body region contacting a bottom surface and at least one sidewall of the source region, and
a drift region of the first conductivity type under the drain region, the drift region contacting a bottom surface and at least one sidewall of the drain region,
the drift region having a portion overlapping with the isolation region and the first active region, and

the semiconductor device further includes a stud region in the drift region of the first active region between the first gate line and the second gate line, the stud region having an impurity concentration than higher than an impurity concentration of the drift region.

16. The semiconductor device of claim 15 , further comprising:
a gate connection line connecting one end of the first gate line and one end of the second gate line facing each other.

17. The semiconductor device of claim 15 , further comprising:
a third active region and a fourth active region are arranged in the first direction with the isolation region interposed therebetween,
wherein the first active region and the third active region are arranged in the second direction,
the second active region and the fourth active region are arranged in the second direction, and
the first gate line and the second gate line extend up to the third active region and the fourth active region, respectively.

18. A semiconductor device, comprising:
a substrate having a body region and a drift region, the substrate including, a source region within the body region, and a drain region within the drift region, wherein the source region, the drain region and the drift region have a conductivity type different than a conductivity type of the body region;
a stud region in the drift region and between the source and drain regions, the stud region having an impurity concentration higher than an impurity concentration in the drift region; and a gate electrode extending over portions of the drift region adjacent to a periphery of the stud region, wherein the semiconductor device further includes at least one of, a channel layer including a material having a lattice constant different than a lattice constant of the substrate; and
an isolation region in the drift region, the isolation region being between the drain region and the stud region.

19. The semiconductor device of claim 18 , wherein the stud region is exposed through an opening in the gate electrode.

20. The semiconductor device of claim 18 , wherein the impurity concentration of the stud region is substantially equal to,
an impurity concentration of the source region and an impurit

Assignees

• Noh Jin-Hyun
• Kim Su-Tae
• Yoo Jae-Hyun
• Lee Byeong-Ryeol
• Jeon Jong-Sung
• Samsung Electronics Co Ltd

Inventors

• Noh Jin-Hyun
• Kim Su-Tae
• Yoo Jae-Hyun
• Lee Byeong-Ryeol
• Jeon Jong-Sung

Classifications

• H10D30/65 Primary

  Lateral DMOS [LDMOS] FETs · CPC title

• H10D84/856

  the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title