Semiconductor device having a gate cutting region and a cross-coupling pattern between gate structures

Patent metadata

Field	Value
Publication number	US-9589899-B2
Application number	US-201514801937-A
Country	US
Kind code	B2
Filing date	Jul 17, 2015
Priority date	Oct 10, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

In a semiconductor device, a first gate structure having a first end portion is formed on a substrate. A second gate structure is formed on the substrate, and has a second end portion opposite to the first end portion of the first gate structure in a diagonal direction. A cross-coupling pattern is formed between the first and second gate structure, and electrically connects the first and second gate structures to each other. A first contact plug directly contacts an upper portion of the first end portion of the first gate structure and a first upper sidewall of the cross-coupling pattern. A second contact plug directly contacts an upper portion of the second end portion of the second gate structure and a second upper sidewall of the cross-coupling pattern. In the semiconductor device, a parasitic capacitance due to the cross-coupling structure may decrease.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first gate structure on a substrate, the first gate structure extending in a first direction and having a first end portion;
a second gate structure on the substrate, the second gate structure extending in the first direction and being spaced apart from the first gate structure, and the second gate structure having a second end portion opposite to the first end portion of the first gate structure in a diagonal direction with respect to the first direction;
a cross-coupling pattern between the first and second gate structures, the cross-coupling pattern contacting sidewalls of the first and second gate structures and electrically connecting the first and second gate structures to each other;
a first contact plug directly contacting an upper portion of the first end portion of the first gate structure and a first upper boundary of the cross-coupling pattern, the first contact plug extending in the first direction; and
a second contact plug directly contacting an upper portion of the second end portion of the second gate structure and a second upper boundary of the cross-coupling pattern, the second contact plug extending in the first direction;
wherein the substrate includes a gate cutting region having a substantially rectangular shape in plan view between first and second gate electrodes, wherein edges of the gate cutting region are adjacent to the first and second end portions of the first and second gate structures, and wherein the cross-coupling pattern is confined within the edges of the gate cutting region.

2. The semiconductor device of claim 1 , wherein top surfaces of the first and second gate structures, the cross-coupling pattern and the first and second contact plugs are substantially coplanar with one another.

3. The semiconductor device of claim 1 , wherein a bottom surface of the cross-coupling pattern is on the substrate.

4. The semiconductor device of claim 1 , wherein the substrate includes active fins, and wherein the first and second gate structures cross the active fins.

5. The semiconductor device of claim 1 , wherein at least one of the first and second gate structures includes a gate insulation layer, a gate electrode and a hard mask in a sequentially stacked configuration, wherein the first contact plug is in contact with a sidewall of the hard mask and a top surface of the gate electrode of the first gate structure, and the second contact plug is in contact with a sidewall of the hard mask and a top surface of the gate electrode of the second gate.

6. The semiconductor device of claim 5 , wherein top surfaces of the first and second contact plugs are substantially coplanar with top surfaces of the hard masks of the first and second gate structures.

7. The semiconductor device of claim 1 , further comprising an insulation layer pattern in the gate cutting region surrounding sidewalls of the cross-coupling pattern.

8. The semiconductor device of claim 7 , wherein the insulation layer pattern includes silicon oxide.

9. The semiconductor device of claim 1 , further comprising:
a third gate structure extending in the first direction and being spaced apart from the first gate structure in the first direction; and
a fourth gate structure extending in the first direction and being spaced apart from the second gate structure in the first direction,
wherein at least one of the third and fourth gate structures is outside of the gate cutting region.

10. The semiconductor device of claim 1 , further comprising spacers on sidewalls of the first and second gate electrodes, wherein at least one of the spacers extends in the first direction.

11. The semiconductor device of claim 1 , wherein the cross-coupling pattern includes a first portion contacting a sidewall of the first end portion of the first gate structure and extending in a third direction, a third portion contacting a sidewall of the second end portion of the second gate structure and extending in the third direction, and a second portion between the first and third portions.

12. The semiconductor device of claim 1 , wherein the cross-coupling pattern and the first and second contact plugs include substantially the same conductive material.

13. A semiconductor device, comprising:
a first gate structure including a first gate electrode and a first hard mask in a sequentially stacked configuration on a substrate, the first gate structure extending in a first direction having a first end portion at which the first gate structure is exposed by the first hard mask;
a second gate structure including a second gate electrode and a second hard mask in a sequentially stacked configuration on the substrate and being spaced apart from the first gate structure, the second gate structure having a second end portion where the second gate structure is exposed by the second hard mask, the second end portion of the second gate structure being opposite to the first end portion of the first gate structure in a diagonal direction;
a cross-coupling pattern between the first and second gate structures, the cross-coupling pattern contacting sidewalls of the first and second gate electrodes and electrically connecting the first and second gate structures to each other;
a first contact plug directly contacting a sidewall of the first hard mask, a top surface of the first gate electrode, and a first upper boundary of the cross-coupling pattern, the first contact plug extending in the first direction; and
a second contact plug directly contacting a sidewall of the second hard mask, a top surface of the second gate electrode, and a second upper boundary of the cross-coupling pattern, the second contact plug extending in the first direction;
wherein the substrate includes a gate cutting region having a substantially rectangular shape in plan view between the first and second gate electrode, wherein edges of the gate cutting region are adjacent to the first and second end portions of the first and second gate structures, and wherein the cross-coupling pattern is confined within the edges of the gate cutting region.

14. The semiconductor device of claim 13 , further comprising a fifth gate structure and a sixth gate structure on a portion of the substrate spaced apart from the gate cutting region, wherein the fifth and sixth gate structures have stacked structures that are substantially the same as stacked structures of the first and second gate structures.

15. A semiconductor device, comprising:
a first gate and a second gate on a substrate the first and second gates extending in a first direction;
a cross-coupling pattern having first sidewalls and second sidewalls, the cross-coupling pattern being between the first and second gates, the first sidewalls of the cross-coupling pattern being in contact with corresponding sidewalls of the first and second gates;
a first contact plug in contact with a first boundary of the cross-coupling pattern, the first contact plug extending in the first direction;
a second contact plug in contact with a second boundary of the cross-coupling pattern, the second contact plug extending in the first direction;
the first contact plug overlapping at least a portion of the first gate and one of the first sidewalls of the cross-coupling pattern;
the second contact plug overlapping at least a portion of the second gate and another of the first sidewalls of the cross-coupling pattern; and
a surface of the cross-coupling pattern being substantially co-planar with surfaces of the first and second contact plugs;
wherein the substrate includes a gate cutting region having a substant

Assignees

• Jun Hwi-Chan
• Weon Dae-Hee
• Shin Heon-Jong
• Lee Yu-Sun
• Samsung Electronics Co Ltd

Inventors

• Jun Hwi-Chan
• Weon Dae-Hee
• Shin Heon-Jong
• Lee Yu-Sun

Classifications

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L27/0886

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic