Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-12512428-B2
Application number	US-202217980740-A
Country	US
Kind code	B2
Filing date	Nov 4, 2022
Priority date	Mar 31, 2022
Publication date	Dec 30, 2025
Grant date	Dec 30, 2025

Abstract

Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises lower and upper structures. The lower structure includes a first semiconductor substrate, a first pad, and a first dielectric layer. The upper structure includes a second semiconductor substrate, a second pad, and a second dielectric layer. The upper and lower structures are bonded to each other to allow the first and second pads to come into contact each other and to allow the first and second dielectric layers to come into contact each other. A first interface between the first and second pads is at a level different from that of a second interface between the first and second dielectric layers. A first area of the first pad is greater than a second area of the second pad. A second thickness of the second pad is different from a first thickness of the first pad.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a lower structure; and an upper structure,
wherein the lower structure includes:
a first semiconductor substrate;
a first pad on the first semiconductor substrate; and
a first dielectric layer that surrounds the first pad on the first semiconductor substrate,

wherein the upper structure includes:
a second semiconductor substrate;
a second pad on the second semiconductor substrate; and
a second dielectric layer that surrounds the second pad on the second semiconductor substrate,

wherein the upper structure and the lower structure are bonded to each other to allow the first pad and the second pad to come into contact each other and to allow the first dielectric layer and the second dielectric layer to come into contact each other,
wherein a first interface between the first pad and the second pad is at a level different from a level of a second interface between the first dielectric layer and the second dielectric layer,
wherein a first area of the first pad is greater than a second area of the second pad, and
wherein a second thickness of the second pad is different from a first thickness of the first pad.

2 . The semiconductor device of claim 1 , wherein, when viewed in a plan view, an entirety of the second pad overlaps at least a portion of the first pad.

3 . The semiconductor device of claim 1 , wherein
the second thickness of the second pad is greater than the first thickness of the first pad, and the first interface is closer than the second interface to the first semiconductor substrate.

4 . The semiconductor device of claim 3 , wherein
the first pad has a first recess directed toward the first semiconductor substrate from a top surface of the first dielectric layer, and the second pad is inserted into the first recess to come into contact with the first pad.

5 . The semiconductor device of claim 3 , wherein the second thickness of the second pad is about 1.5 times to about 3 times the first thickness of the first pad.

6 . The semiconductor device of claim 1 , wherein
the first thickness of the first pad is greater than the second thickness of the second pad, and the second interface is closer than the first interface to the first semiconductor substrate.

7 . The semiconductor device of claim 6 , wherein
the second pad has a second recess directed toward the second semiconductor substrate from a bottom surface of the second dielectric layer, and the first pad is inserted into the second recess to come into contact with the second pad.

8 . The semiconductor device of claim 1 , wherein the first area of the first pad is about 1.5 times to about 2 times the second area of the second pad.

9 . The semiconductor device of claim 1 , wherein
the first pad and the second pad include copper (Cu), and the first dielectric layer and the second dielectric layer include oxide, nitride, or oxynitride of a material included in the first and second semiconductor substrates.

10 . The semiconductor device of claim 1 , wherein each of the first and second pads has a circular planar shape or a rectangular planar shape.

11 . The semiconductor device of claim 10 , wherein a width of the first pad is in a range of about 2 μm to about 30 μm.

12 . The semiconductor device of claim 1 , wherein
the first pad has a rectangular planar shape or a linear planar shape, the second pad has a rectangular planar shape or a linear planar shape, and when viewed in a plan view, the first pad and the second pad are disposed in a cross shape where the first pad and the second pad intersect each other.

13 . A semiconductor device, comprising:
a lower structure including a first circuit pattern on a first substrate, a first dielectric layer that covers the first circuit pattern on the first substrate, and a first pad that is exposed on the first dielectric layer and is connected to the first circuit pattern; and an upper structure including a second circuit pattern on a second substrate, a second dielectric layer that covers the second circuit pattern on the second substrate, and a second pad that is exposed on the second dielectric layer and is connected to the second circuit pattern,
wherein a top surface of the first pad has a recess directed toward the first substrate,
wherein a portion of the second pad extends into the recess to come into contact with the first pad, and the first pad and the second pad constitute a single unitary body formed of a same material, and
wherein a second thickness of the second pad is greater than a first thickness of the first pad.

14 . The semiconductor device of claim 13 , wherein a first interface between the first pad and the second pad is closer to the first substrate than a second interface between the first dielectric layer and the second dielectric layer.

15 . The semiconductor device of claim 13 , wherein a first area of the first pad is greater than a second area of the second pad.

16 . The semiconductor device of claim 13 , wherein, when viewed in a plan view, an entirety of the second pad overlaps at least a portion of the first pad.

17 . The semiconductor device of claim 13 , further comprising:
a memory cell array in the lower structure, wherein the memory cell array includes a plurality of cell strings including a plurality of memory cells, a plurality of word lines connected to corresponding memory cells, a plurality of bit lines connected to corresponding sides of the cell strings, and a ground selection line connected to the cell strings; a control circuit in the upper structure, wherein the control circuit includes a free charge control circuit that controls ones of the cell strings and controls a plurality of data program steps for the memory cells; and a row decoder in the upper structure, wherein in response to control of the control circuit, the row decoder activates at least one of the word lines.

18 . A method of fabricating a semiconductor device, the method comprising:
providing a lower structure that includes a first semiconductor substrate, a first pad on the first semiconductor substrate, and a first dielectric layer surrounding the first pad on the first semiconductor substrate; performing a planarization process on the first pad and the first dielectric layer, a recess being formed on a top surface of the first pad after the planarization process, the recess being at a level lower than a level of a top surface of the first dielectric layer; providing an upper structure that includes a second semiconductor substrate, a second pad on the second semiconductor substrate, and a second dielectric layer surrounding the second pad on the second semiconductor substrate; causing the upper structure and the lower structure to contact each other to allow the first pad and the second pad to vertically align with each other and to allow the first dielectric layer and the second dielectric layer to be coupled to each other; and performing an annealing process on the upper structure and the lower structure, wherein, during the annealing process, the second pad expands toward the first pad so as to fill the recess, and the second pad and the first pad are brought into contact and bonded to each other.

19 . The method of claim 18 , wherein
a first area of the first pad is greater than a second area of the second pad, and a second thickness of the second pad is greater than a first thickness of the first pad.

20 . The method of claim 18 ,

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jihoon
• Kim Minki
• Lee Wonil
• Lee Hyuekjae

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/033

  by chemical means, e.g. etching · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title