Semiconductor package and method of forming the same

Patent metadata

Field	Value
Publication number	US-10026704-B2
Application number	US-201715707700-A
Country	US
Kind code	B2
Filing date	Sep 18, 2017
Priority date	Sep 22, 2016
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

First claim

What is claimed is:

1. A structure comprising:
a first substrate comprising a first passive device embedded in the first substrate;
a first dielectric layer over a first side of the first substrate;
a first plurality of bond pads in the first dielectric layer, a first surface of the first dielectric layer being level with first surfaces of the first plurality of bond pads; and
a first die comprising:
a second plurality of bond pads bonded to the first plurality of bond pads through metal-to-metal bonding; and
a second plurality of dielectric layers comprising a second dielectric layer, with the second dielectric layer having a second surface level with second surfaces of the second plurality bond pads, the first dielectric layer being bonded to the second dielectric layer through dielectric-to-dielectric bonds.

2. The structure of claim 1 , wherein the second dielectric layer extends laterally beyond respective edges of the first dielectric layer.

3. The structure of claim 1 , wherein the first dielectric layer is bonded to the second dielectric layer with respective bonds comprising O—H bonds.

4. The structure of claim 1 further comprising:
a first redistribution structure over a first side of the first substrate, the first redistribution structure comprising first metallization patterns in a first plurality of dielectric layers, the first plurality of dielectric layers comprising the first dielectric layer, the first metallization patterns comprising the first plurality of bond pads.

5. The structure of claim 4 further comprising:
a first electrical connector adjacent the first die and on one of the first metallization patterns, the first electrical connector being electrically coupled to the one of the first metallization patterns;
a first encapsulant on the first redistribution structure, the first encapsulant at least laterally encapsulating the first electrical connector and the first die; and
a second redistribution structure over the first encapsulant, the second redistribution structure comprising third metallization patterns, at least one of the third metallization patterns being electrically coupled to the first electrical connector.

6. The structure of claim 5 further comprising:
a package structure over and bonded to the first electrical connector with a first bonding joint, the package structure comprising a second die.

7. The structure of claim 5 further comprising:
a second die over the second redistribution structure;
a second electrical connector adjacent the second die and on one of the third metallization patterns, the second electrical connector being electrically coupled to the one of the third metallization patterns;
a second encapsulant on the second redistribution structure, the second encapsulant at least laterally encapsulating the second electrical connector and the second die; and
a third redistribution structure over the second encapsulant, the third redistribution structure comprising fourth metallization patterns, at least one of the fourth metallization patterns being electrically coupled to the second electrical connector.

8. The structure of claim 7 , wherein an active side of the second die is distal the second redistribution structure and a backside of the second die is proximate the second redistribution structure.

9. The structure of claim 1 further comprising:
a first interconnect structure on the first die, the first interconnect structure comprising second metallization patterns in a second plurality of dielectric layers, the second plurality of dielectric layers comprising the second dielectric layer, the second metallization patterns comprising the second plurality of bond pads.

10. The structure of claim 1 further comprising:
a first through via extending through the first substrate, the first through via being electrically coupled to one of the first plurality of bond pads.

11. The structure of claim 1 , wherein the first passive device comprises a capacitor, a resistor, an inductor, or a combination thereof.

12. A method comprising:
forming a through via extending into a first wafer from a first side;
forming a first passive device in the first wafer, the first passive device and the through via being formed in same processing steps;
forming a first dielectric layer over the first side of the first wafer;
forming a first plurality of bond pads in the first dielectric layer;
planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other;
forming a first electrical connector on one of the first plurality of bond pads;
bonding a second plurality of bond pads of a first device die to at least some of the first plurality of bond pads;
bonding a second dielectric layer of the first device die to the first dielectric layer;
encapsulating the first device die and the first electrical connector in a first encapsulant; and
singulating the encapsulant and the first wafer.

13. The method of claim 12 , wherein forming an electrical connector on one of the first plurality of bond pads;
comprises:
before the encapsulating, plating the first electrical connector on the one of the first plurality of bond pads.

14. The method of claim 12 further comprising:
forming a third dielectric layer over the first device die, the first electrical connector, and the first encapsulant;
forming a third plurality of bond pads in the third dielectric layer, at least one of the third plurality of bond pads being electrically coupled to the first electrical connector; and
bonding a package structure to the third plurality of bond pads.

15. The method of claim 12 further comprising:
forming a third dielectric layer over the first device die, the first electrical connector, and the first encapsulant;
forming a third plurality of bond pads in the third dielectric layer, at least one of the third plurality of bond pads being electrically coupled to the first electrical connector; and
forming a second electrical connector on one of the third plurality of bond pads;
attaching a second device die over the third dielectric layer;
laterally encapsulating the second device die and the second electrical connector in a second encapsulant;
forming a fourth dielectric layer over the second device die, the second electrical connector, and the second encapsulant; and
forming a first metallization pattern in the fourth dielectric layer, the first metallization pattern electrically coupled to the second electrical connector and the second device die.

16. The method of claim 12 further comprising:
thinning a second side of the first wafer to expose an end of the through via; and
forming a conductive connector on the exposed end of the through via.

17. The method of claim 12 , wherein the first passive device comprises a capacitor, a resistor, an inductor, or a combination thereof.

18. A method comprising:
forming a first package comprising:
forming a passive device and a through via in a first wafer, the passive device comprising a capacitor, a resistor, an inductor, or a combination thereof;
forming a first redistribution structure over a first side of the first wafer, the first redistribution structure comprising a first plurality of bond pads in a first dielectric layer, top surfaces of the first plurality of bond pads level with a top surface of the first dielectric layer;
forming a first electrical connector on one of the first plurality of bond pads;
bonding a

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Chi-Hsi
• Yeh Der-Chyang
• Chen Hsien-Wei
• Chen Jie

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/0198

  batch processes · CPC title