Semiconductor package

Patent metadata

Field	Value
Publication number	US-11848293-B2
Application number	US-202117376616-A
Country	US
Kind code	B2
Filing date	Jul 15, 2021
Priority date	Sep 22, 2020
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

A semiconductor package includes a sequential stack of first and second semiconductor chips, and a first internal connection member that connects the first and second semiconductor chips to each other. The first semiconductor chip includes a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and a first conductive pad on the first top surface. The second semiconductor chip includes a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and a second conductive bump on the second bottom surface. The first internal connection member connects the first conductive pad to the second conductive bump. The first conductive pad has a first width in one direction. The second conductive bump has a second width in the one direction. The first width is smaller than the second width.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a sequential stack of a first semiconductor chip and a second semiconductor chip; and
a first internal connection member that connects the first semiconductor chip to the second semiconductor chip,
wherein the first semiconductor chip includes
a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and
a first conductive pad on the first top surface, wherein the second semiconductor chip includes
a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and
a conductive bump below the second bottom surface,

wherein the first internal connection member connects the first conductive pad of the first semiconductor chip to the conductive bump of the second semiconductor chip,
wherein the first conductive pad has a first width in one direction,
wherein the conductive bump has a second width in the one direction, and
wherein the first width is smaller than the second width.

2. The semiconductor package of claim 1 , wherein a magnitude of the first width is about 80% to 90% of a magnitude of the second width.

3. The semiconductor package of claim 1 , wherein
the first conductive pad and the conductive bump include a first metal,
the first internal connection member includes the first metal and further includes second, third, and fourth metals,
the first internal connection member includes first, second, third, fourth, and fifth connection regions that are sequentially stacked,
each of the first and fifth connection regions includes the first metal and the second metal, and excludes both the third metal and the fourth metal,
the third connection region includes the second metal and the third metal, and excludes both the first metal and the fourth metal, and
each of the second and fourth connection regions includes the first metal, the second metal, and the fourth metal, and excludes the third metal.

4. The semiconductor package of claim 3 , wherein
the first metal includes nickel (Ni),
the second metal includes tin (Sn),
the third metal includes silver (Ag), and
the fourth metal includes gold (Au).

5. The semiconductor package of claim 3 , wherein
the first connection region contacts the first conductive pad,
the fifth connection region contacts the conductive bump,
the second connection region has a first average thickness,
the fourth connection region has a second average thickness, and
the first average thickness is greater than the second average thickness.

6. The semiconductor package of claim 1 , wherein
the first conductive pad has a first thickness,
the conductive bump has a second thickness, and
the second thickness is greater than the first thickness.

7. The semiconductor package of claim 1 , wherein the second semiconductor chip further includes a second conductive pad between the second substrate and the conductive bump, the second conductive pad being in contact with the conductive bump,
wherein the second conductive pad has a third width in the one direction,
wherein the third width is greater than the second width.

8. The semiconductor package of claim 1 , wherein
the first semiconductor chip further includes a through via that penetrates the first substrate, the through via being in contact with the first conductive pad,
wherein the through via has a third width in the one direction,
wherein the third width is smaller than the first width.

9. The semiconductor package of claim 1 , further comprising:
a first dielectric layer between the first conductive pad and the first substrate; and
a first redistribution pattern that includes a via part and a pad part, the via part penetrating the first dielectric layer, and the pad part protruding onto the first dielectric layer,
wherein the first conductive pad is in contact with the pad part, and
wherein a sidewall of the pad part is aligned with a sidewall of the first conductive pad.

10. The semiconductor package of claim 1 , further comprising:
an under-fill layer between the first semiconductor chip and the second semiconductor chip,
wherein the under-fill layer is in simultaneous contact with a sidewall of the first conductive pad, a sidewall of the conductive bump, and a sidewall of the first internal connection member.

11. The semiconductor package of claim 10 , wherein the first semiconductor chip further includes:
a plurality of first wiring lines on the first bottom surface;
a first interlayer dielectric layer that covers the first wiring lines;
a first passivation layer that covers the first top surface; and
a first through via that penetrates the first substrate and the first passivation layer,
wherein the first conductive pad contacts the first through via, and
wherein the under-fill layer contacts a top surface of the first passivation layer.

12. A semiconductor package, comprising:
a sequential stack of a first semiconductor chip and a second semiconductor chip; and
a first internal connection member that connects the first semiconductor chip to the second semiconductor chip,
wherein the first semiconductor chip includes
a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and
a first conductive pad on the first top surface, wherein the second semiconductor chip includes
a second substrate that has a second top surface and a second bottom surface that are opposite to each other,
a second conductive pad adjacent to the second bottom surface, and
a conductive bump bonded to and below the second conductive pad,

wherein the first internal connection member connects the first conductive pad to the conductive bump,
wherein the first internal connection member includes:
a first connection region adjacent to the first conductive pad, and
a second connection region adjacent to the conductive bump,

wherein each of the first and second connection regions includes gold (Au),
wherein the first connection region has a first average thickness, and
wherein the second connection region has a second average thickness smaller than the first average thickness.

13. The semiconductor package of claim 12 , wherein
the first conductive pad has a first width in one direction,
the conductive bump has a second width in the one direction, and
the first width is smaller than the second width.

14. The semiconductor package of claim 12 , wherein the first internal connection member further includes
a third connection region between the first conductive pad and the first connection region;
a fourth connection region between the first connection region and the second connection region; and
a fifth connection region between the fourth connection region and the conductive bump,
wherein all of the first conductive pad, the conductive bump, and the third to fifth connection regions exclude gold,
wherein each of the first conductive pad and the conductive bump includes a first metal,
wherein each of the third and fifth connection regions includes the first metal and a second metal,
wherein the fourth connection region includes the second metal and a third metal, and excludes the first metal, and
wherein each of the first and second connection regions further includes the first metal and the second metal, and excludes the third metal.

15. The semiconductor package of claim 12 , wherein a width of the first internal connection member narrows with increased proximity to the first conductive pad.

16. The semiconductor package of claim

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Sunkyoung
• Lee Teak Hoon
• Jo Chajea

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W20/0249

  wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title