Hybrid bond using a copper alloy for yield improvement

Patent metadata

Field	Value
Publication number	US-9728521-B2
Application number	US-201514806888-A
Country	US
Kind code	B2
Filing date	Jul 23, 2015
Priority date	Jul 23, 2015
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

An integrated circuit (IC) using a copper-alloy based hybrid bond is provided. The IC comprises a pair of semiconductor structures vertically stacked upon one another. The pair of semiconductor structures comprise corresponding dielectric layers and corresponding metal features arranged in the dielectric layers. The metal features comprise a copper alloy having copper and a secondary metal. The IC further comprises a hybrid bond arranged at an interface between the semiconductor structures. The hybrid bond comprises a first bond bonding the dielectric layers together and a second bond bonding the metal features together. The second bond comprises voids arranged between copper grains of the metal features and filled by the secondary metal. A method for bonding a pair of semiconductor structures together using the copper-alloy based hybrid bond is also provided.

First claim

What is claimed is:

1. A method for bonding a pair of semiconductor structures together, the method comprising:
providing a pair of semiconductor structures comprising corresponding dielectric layers and corresponding metal features arranged in the dielectric layers, wherein the metal features comprise a copper alloy having copper and a secondary metal, and wherein the metal features comprise a metal feature of the copper alloy;
bonding the semiconductor structures together to form a hybrid bond at an interface between the semiconductor structures, the hybrid bond comprising a first bond bonding the dielectric layers together, a second bond bonding the metal features together, and a third bond bonding one of the dielectric layers to the metal feature, and wherein the second bond comprises voids arranged between copper grains of the metal features; and
performing an anneal to the hybrid bond to form regions of the secondary metal along boundaries of the copper grains, to fill the voids with the secondary metal, and to fill additional voids of the third bond with the secondary metal.

2. The method according to claim 1 , wherein the metal features comprise a second metal feature of pure copper, and wherein the bonding the semiconductor structures together comprises:
bonding the metal feature to the second metal feature with the second bond.

3. The method according to claim 1 , further comprising:
forming the copper alloy with a secondary metal that has an atomic weight less than that of copper, solubility in copper, and an atomic size difference with copper that is less than about 10%.

4. The method according to claim 1 , further comprising:
forming the copper alloy with a secondary metal of aluminum, titanium, nickel, cobalt, manganese, zirconium, or hafnium.

5. The method according to claim 1 , wherein the providing the pair of semiconductor structures comprises:
providing a semiconductor structure comprising a dielectric layer;
performing an etch into the dielectric layer to form an opening for the metal feature;
forming a diffusion barrier layer lining the opening;
forming a seed layer of the copper alloy lining the opening over the diffusion barrier layer;
forming a fill layer of copper filling the opening over the seed layer; and
performing a chemical mechanical polish (CMP) into the diffusion barrier layer, the seed layer, and the fill layer to coplanarize upper surfaces of the diffusion barrier layer, the seed layer, and the fill layer with an upper surface of the dielectric layer, and to form the metal feature.

6. The method according to claim 5 , further comprising:
before the performing the CMP, performing a second anneal of the seed layer and the fill layer to interdiffuse the copper alloy of the seed layer with the copper of the fill layer.

7. The method according to claim 5 , further comprising:
performing the etch into the dielectric layer to form the opening for a pair of metal features of a dual damascene structure; and
performing the CMP into the diffusion barrier layer, the seed layer, and the fill layer to form the pair of metal features for the dual damascene structure.

8. The method according to claim 1 , further comprising:
forming the dielectric layers of silicon oxynitride, oxide, or silicon nitride.

9. The method according to claim 1 , wherein the semiconductor structures are integrated circuits, and wherein the method further comprises:
bonding the semiconductor structures together through corresponding back end of line (BEOL) metallization stacks to form the hybrid bond.

10. A method for bonding a pair of semiconductor structures together, the method comprising:
providing a pair of semiconductor structures comprising dielectric layers and metal features arranged in the dielectric layers, wherein the metal features comprise a primary metal that is pure, and wherein at least one of the metal features is a metal alloy, comprising the primary metal and a secondary metal; and
forming a hybrid bond interface between the semiconductor structures, wherein the forming the hybrid bond interface comprises forming a first bond interface between the dielectric layers, and further forming a second bond interface between the metal features, and wherein the second bond interface is formed with the secondary metal filling voids between metal grains of the metal features;
wherein the providing the pair of semiconductor structures comprises:
performing an etch into a first dielectric layer of the dielectric layers to form an opening for a first metal feature of the metal features;
forming a seed layer of the metal alloy lining the opening;
forming a fill layer of the primary metal filling the opening over the seed layer;
performing an anneal of the seed and fill layers to interdiffuse the seed and fill layers, such that the fill layer becomes the metal alloy; and
performing a chemical mechanical polish (CMP) into the interdiffused seed and fill layers to form the first metal feature.

11. The method according to claim 10 , wherein the primary metal is pure copper, and wherein the secondary metal has an atomic weight less than that of copper, solubility in copper, and an atomic size difference with copper that is less than about 10%.

12. The method according to claim 10 , wherein the forming the second bond interface comprises:
bonding the metal features together using a metallic bonding process, wherein the voids are unfilled after the bonding; and
performing an anneal to the metal features to form precipitates of the secondary metal from the metal alloy, wherein the precipitates are formed filling the voids.

13. The method according to claim 12 , wherein the precipitates are formed with an elevated concentration at the second bond interface relative to interiors of the metal features.

14. The method according to claim 10 , wherein the providing the pair of semiconductor structures comprises:
forming a diffusion barrier layer lining the opening, wherein the seed layer is formed lining the opening over the diffusion barrier layer, wherein the CMP is further performed into the diffusion barrier layer, wherein the CMP coplanarizes upper surfaces respectively of the diffusion barrier layer, the seed layer, and the fill layer with an upper surface of the first dielectric layer, and wherein the primary metal is pure copper.

15. The method according to claim 14 , wherein the providing the pair of semiconductor structures further comprises:
forming the first dielectric layer covering a semiconductor substrate and a device region, wherein the device region is arranged over and within the semiconductor substrate; and
forming an alternating stack of metal lines and vias overlying the semiconductor substrate and the device region, and within the first dielectric layer, while forming the first dielectric layer, wherein the seed and fill layers are formed electrically coupled to the device region through the metal lines and the vias.

16. The method according to claim 10 , wherein the forming the hybrid bond interface further comprises:
forming a third bond interface between the at least one of the metal features and the dielectric layers, wherein the third bond interface is formed with the secondary metal filling additional voids between the at least one of the metal features and the dielectric layers.

17. The method according to claim 16 , wherein the forming the third bond interface comprises:
performing an anneal to the at least one of the metal features to form precipitates of the secondary metal from the metal alloy, wherein the preci

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Yu-Cheng
• Chuang Chun-Chieh
• Wang Ching-Chun
• Yaung Dun-Nian
• Hung Feng-Chi
• Huang Chih-Hui
• Lu Yan-Chih
• Chen Ju-Shi

Classifications

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/921

  Structures or relative sizes of bond pads · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title