Methods of reducing parasitic capacitance in semicondutor devices

Patent metadata

Field	Value
Publication number	US-12484292-B2
Application number	US-202418738707-A
Country	US
Kind code	B2
Filing date	Jun 10, 2024
Priority date	Aug 31, 2018
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

A method includes providing a workpiece including a gate structure (MG), a first spacer along a sidewall of the MG, a second spacer along a sidewall of the first spacer, and a source/drain (S/D) feature adjacent to the second spacer. The method further includes forming a contact trench over the S/D feature, removing the second spacer to form an air gap between the MG and the S/D feature, depositing a first dielectric layer over the S/D feature and partially filling the air gap, removing a portion of the first dielectric layer to expose a central portion of a top surface of the S/D feature while a side portion of the top surface of the S/D feature remains under the first dielectric layer, forming an S/D contact in the contact trench, removing the first dielectric layer to extend the air gap, and depositing a second dielectric layer over the air gap.

First claim

What is claimed is:

1 . A method, comprising:
providing a workpiece including a metal gate structure (MG), a first gate spacer disposed along a sidewall of the MG, a second gate spacer disposed along a sidewall of the first gate spacer, and a source/drain (S/D) feature disposed adjacent to the second gate spacer; forming a contact trench over the S/D feature; removing the second gate spacer to form an air gap between the MG and the S/D feature; depositing a first dielectric layer over the S/D feature and partially filling the air gap; removing a first portion of the first dielectric layer to expose a central portion of a top surface of the S/D feature, wherein a side portion of the top surface of the S/D feature remains under the first dielectric layer; forming an S/D contact in the contact trench; removing at least a second portion of the first dielectric layer to extend the air gap; and depositing a second dielectric layer over the air gap.

2 . The method of claim 1 , wherein the workpiece further includes an etch stop layer (ESL) disposed over the S/D feature and along a sidewall of the second gate spacer,
wherein removing the second gate spacer to form the air gap further removes a portion of the ESL disposed along the sidewall of the second gate spacer.

3 . The method of claim 1 , wherein the first dielectric layer includes a first sublayer and a second sublayer disposed over the first sublayer,
wherein the first sublayer partially fills the air gap, and wherein removing the first portion of the first dielectric layer removes the first portion from both the first sublayer and the second sublayer.

4 . The method of claim 3 , wherein removing at least the second portion of the first dielectric layer to extend the air gap includes removing the first sublayer or removing both the first sublayer and the second sublayer.

5 . The method of claim 3 , wherein removing at least the second portion of the first dielectric layer to extend the air gap includes:
replacing the second sublayer with a third dielectric layer, and removing the first sublayer.

6 . The method of claim 3 , wherein the second sublayer includes a greater amount of nitrogen than the first sublayer.

7 . The method of claim 1 , wherein forming the S/D contact in the contact trench includes:
forming a silicide layer in a bottom of the trench, wherein the silicide layer contacts the central portion of the top surface of the S/D feature, and forming the S/D contact over the silicide layer.

8 . The method of claim 1 , wherein depositing the second dielectric layer over the air gap includes partially filling the air gap with the second dielectric layer.

9 . A method, comprising:
providing a workpiece including a metal gate structure (MG), a source/drain (S/D) feature disposed adjacent to the MG, a dielectric structure disposed over the S/D feature, and a gate spacer disposed between the S/D feature and the MG and between the dielectric structure and the MG; forming a trench in the dielectric structure and exposing the S/D feature; removing a portion of the gate spacer to form an air gap between the MG and the S/D feature; depositing a first dielectric layer over the S/D feature, the MG, and a remaining portion of the gate spacer; removing a portion of the first dielectric layer to expose a first portion of a top surface of the S/D feature, wherein a second portion of the top surface of the S/D feature remains unexposed; forming an S/D contact in the trench; removing the first dielectric layer; and depositing a second dielectric layer in a top portion of the air gap.

10 . The method of claim 9 , wherein forming the S/D contact in the trench includes:
forming a silicide layer in a bottom of the trench, and forming the S/D contact over the silicide layer in the trench.

11 . The method of claim 10 , after forming the silicide layer in the bottom of the trench, further comprising removing a top portion of the first dielectric layer to form a rounded profile of the first dielectric layer.

12 . The method of claim 9 , wherein depositing the first dielectric layer includes partially filling the air gap with the first dielectric layer.

13 . The method of claim 9 , wherein the portion of the first dielectric layer is a first portion of the first dielectric layer,
wherein removing the first dielectric layer includes removing a second portion of the first dielectric layer from a sidewall of the MG.

14 . The method of claim 13 , wherein removing the first dielectric layer further includes removing a third portion of the first dielectric layer from a sidewall of the S/D contact.

15 . The method of claim 9 , wherein the portion of the first dielectric layer is a first portion of the first dielectric layer and the air gap is a first air gap,
wherein removing the first dielectric layer includes removing a second portion of the first dielectric layer from a sidewall of the S/D contact to leave a second air gap, depositing a third dielectric layer in the second air gap, and removing a third portion of the first dielectric layer from a sidewall of the MG.

16 . A semiconductor structure, comprising:
a semiconductor fin; a source/drain (S/D) feature disposed over the semiconductor fin; a contact structure disposed over the S/D feature, wherein the contact structure has a continuous bottom surface, wherein a first portion of the continuous bottom surface interfaces with the S/D feature; and an air gap disposed between a second portion of the continuous bottom surface of the contact structure and a top surface of the S/D feature.

17 . The semiconductor structure of claim 16 , wherein the air gap is a first air gap,
wherein the semiconductor structure further comprises a second air gap disposed along sidewalls of the S/D feature and the contact structure, and wherein the first air gap and the second air gap are connected.

18 . The semiconductor structure of claim 17 , further comprising a spacer layer disposed along a sidewall of the contact structure,
wherein a sidewall of the spacer layer is exposed to the second air gap.

19 . The semiconductor structure of claim 16 , further comprising:
a metal gate structure adjacent to the S/D feature; and a gate spacer disposed between the contact structure and the metal gate structure and between the S/D feature and the metal gate structure.

20 . The semiconductor structure of claim 16 , wherein the contact structure includes a silicide layer and an S/D contact disposed over the silicide layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• LEE Kai-Hsuan
• Yang Feng-Cheng
• Chen Yen-Ming
• Yeong Sai-Hooi

Classifications

• H10P95/064

  the removal being chemical etching · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title