Contact over active gate employing a stacked spacer

Patent metadata

Field	Value
Publication number	US-2019312123-A1
Application number	US-201815949634-A
Country	US
Kind code	A1
Filing date	Apr 10, 2018
Priority date	Apr 10, 2018
Publication date	Oct 10, 2019
Grant date	—

Abstract

A method is presented for employing contact over active gate to reduce parasitic capacitance. The method includes forming high-k metal gates (HKMGs) between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion, forming a first dielectric over the HKMGs, forming first contacts to source/drain of a transistor between the HKMGs, and forming a second dielectric over the first contacts. The method further includes selectively removing the first dielectric to form second contacts to the HKMGs, selectively removing the second dielectric to form third contacts on top of the first contacts, removing the sacrificial upper portion of the stacked spacers, and depositing a third dielectric that pinches off the remaining first and second dielectrics to form air-gaps between the first contacts and the HKMGs.

First claim

1 . A method for employing contact over active gate to reduce parasitic capacitance, the method comprising:
forming high-k metal gates (HKMGs) between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion; forming a first dielectric over the HKMGs; forming first contacts to a source/drain of a transistor between the HKMGs; forming a second dielectric over the first contacts; selectively removing the first dielectric to form second contacts to the HKMGs; selectively removing the second dielectric to form third contacts on top of the first contacts; removing the sacrificial upper portion of the stacked spacers; and depositing a third dielectric that pinches off the remaining first and second dielectrics to form air-gaps between the first contacts and the HKMGs.

2 . The method of claim 1 , wherein the low-k dielectric lower portion defines a first length and the sacrificial upper portion defines a second length, where the second length is greater than the first length.

3 . The method of claim 1 , wherein the first dielectric has a first thickness and the second dielectric has a second thickness, the first and second thickness being different from each other.

4 . The method of claim 1 , further comprising forming the sacrificial upper portion from amorphous silicon (α-Si).

5 . The method of claim 1 , wherein the air-gaps extend parallel to a portion of the HKMGs and a portion of the first and second dielectrics.

6 . The method of claim 1 , wherein the sacrificial upper portion enables physical isolation between the second and third contacts.

7 . The method of claim 1 , wherein the third dielectric wraps around the first and second dielectrics.

8 . A method for reducing parasitic capacitance, the method comprising:
forming high-k metal gates (HKMGs) between spacers having an upper portion and a lower portion; forming metal gate caps over the HKMGs; forming first contacts to a source/drain of a transistor between the HKMGs; forming dielectric caps over the first contacts; selectively removing the metal gate caps to form second contacts to the HKMGs; selectively removing the dielectric caps to form third contacts on top of the first contacts; removing the upper portion of the spacers to form openings; and depositing a dielectric in the openings to form air-gap spacers with gate contact over active device region.

9 . The method of claim 8 , wherein the lower portion of the spacers is a low-k dielectric and the upper portion of the spacers is a sacrificial amorphous silicon (α-Si).

10 . The method of claim 9 , wherein the low-k dielectric portion defines a first length and the α-Si sacrificial upper portion defines a second length, where the second length is greater than the first length.

11 . The method of claim 8 , wherein the metal gate caps have a first thickness and the dielectric caps have a second thickness, the first and second thickness being different from each other.

12 . The method of claim 8 , wherein the air-gaps extend parallel to a portion of the HKMGs and a portion of the metal gate caps and the dielectric caps.

13 . The method of claim 8 , wherein the upper portion of the spacers enables physical isolation between the second and third contacts.

14 . The method of claim 8 , wherein the dielectric wraps around the metal gate caps and the dielectric caps.

15 . A semiconductor structure for employing contact over active gate to reduce parasitic capacitance, the semiconductor structure comprising:
high-k metal gates (HKMGs) disposed between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion; a first dielectric disposed over the HKMGs; first contacts directly contacting source/drain regions of a transistor; a second dielectric disposed over second contacts; the second contacts and third contacts created after selective removal of the first and second dielectrics, respectively; and a third dielectric disposed over the remaining first and second dielectrics to create air-gaps between the first contacts and the HKMGs, the air-gaps overlapping a portion of sidewalls of the first contact such that air-gaps on opposed ends of the first contact are aligned over a common source/drain region.

16 . The semiconductor structure of claim 15 , wherein the low-k dielectric lower portion defines a first length and the sacrificial upper portion defines a second length, where the second length is greater than the first length.

17 . The semiconductor structure of claim 15 , wherein the first dielectric has a first thickness and the second dielectric has a second thickness, the first and second thickness being different from each other.

18 . The semiconductor structure of claim 15 , wherein the sacrificial upper portion is constructed from amorphous silicon (α-Si).

19 . The semiconductor structure of claim 15 , wherein the air-gaps extend parallel to a portion of the HKMGs and a portion of the first and second dielectrics.

20 . The semiconductor structure of claim 15 , wherein the sacrificial upper portion enables physical isolation between the second and third contacts.

Assignees

• IBM

Inventors

• Cheng Kangguo

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title