Semiconductor memory device performing recursive ZQ calibration and calibration method thereof

Patent metadata

Field	Value
Publication number	US-12483243-B2
Application number	US-202318381611-A
Country	US
Kind code	B2
Filing date	Oct 18, 2023
Priority date	Jan 2, 2023
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

A semiconductor memory device may include an impedance adjustment pad, a dummy pull-down driver and an external resistor connected in parallel between the impedance adjustment pad and a ground, a recursive code generation circuit configured to recursively generate a pull-up code and a pull-down code corresponding to a target resistance by using the external resistor and the dummy pull-down driver as a reference resistance, in an impedance calibration operation of the semiconductor memory device, a code register configured to store the generated pull-up code and the pull-down code, and a calibration control logic circuit configured to control the recursive code generation circuit during a plurality of steps in the impedance calibration operation while adjusting a resistance value of the dummy pull-down driver.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
an impedance adjustment pad; a dummy pull-down driver and an external resistor connected in parallel between the impedance adjustment pad and a ground; a recursive code generation circuit configured to recursively generate a pull-up code and a pull-down code corresponding to a target resistance by using the external resistor and the dummy pull-down driver as a reference resistance, in an impedance calibration operation of the semiconductor memory device; a code register configured to store the generated pull-up code and the pull-down code; and a calibration control logic circuit configured to control the recursive code generation circuit during a plurality of steps in the impedance calibration operation while adjusting a resistance value of the dummy pull-down driver.

2 . The semiconductor memory device of claim 1 , wherein the dummy pull-down driver includes a plurality of transistors having different aspect ratios connected in parallel between the impedance adjustment pad and the ground.

3 . The semiconductor memory device of claim 1 , wherein, the recursive code generation circuit is configured to deactivate the dummy pull-down driver in a first step among the plurality of steps.

4 . The semiconductor memory device of claim 3 , wherein, in a current step among the plurality of steps, the dummy pull-down driver is configured to set a resistance value in response to a pull-down code generated in a previous step among the plurality of steps.

5 . The semiconductor memory device of claim 4 , wherein a resistance value of the reference resistance corresponds to a value obtained by dividing a resistance value of the external resistor by the number of steps.

6 . The semiconductor memory device of claim 1 , wherein the recursive code generation circuit comprises:
a first comparator configured to compare a voltage distributed to the impedance adjustment pad with a reference voltage; a first counter configured to count up or count down according to the comparison of the first comparator; a pull-up driver connected between the impedance adjustment pad and a power supply voltage and configured to set a resistance value in response to a count value of the first counter as a pull-up code; a replica pull-up driver configured to set a resistance value in response to the pull-up code determined by the first counter; a pull-down driver connected between the replica pull-up driver and the ground; a second comparator configured to compare a voltage on a node connected to the replica pull-up driver and the pull-down driver with the reference voltage; and a second counter configured to set the pull-down driver to a pull-down code that counts up or counts down according to the comparison of the second comparator.

7 . The semiconductor memory device of claim 6 , wherein the reference voltage is half of the power supply voltage.

8 . The semiconductor memory device of claim 7 , wherein the pull-up code determined by the first counter and the pull-down code determined by the second counter are stored in the code register at every step.

9 . The semiconductor memory device of claim 1 , wherein the target resistance is provided through a set feature command provided from an outside of the semiconductor memory device.

10 . The semiconductor memory device of claim 1 , wherein the code register comprises:
a pull-up code register configured to store the pull-up code generated as a result of executing each of the plurality of steps; and a pull-down code register configured to store the pull-down code generated as a result of executing each of the plurality of steps.

11 . An impedance calibration method of a semiconductor memory device, the impedance calibration method comprising:
receiving a target resistance and a calibration command; generating a first pull-up code and a first pull-down code by calibrating a pull-up driver and a pull-down driver using an external resistance connected to an impedance adjustment pad as a reference resistance; setting a dummy pull-down driver connected in parallel to the external resistance between the impedance adjustment pad and a ground to the first pull-down code; and generating a second pull-up code and a second pull-down code by calibrating the pull-up driver and the pull-down driver using a parallel resistance value of the external resistance and the dummy pull-down driver as the reference resistance.

12 . The impedance calibration method of claim 11 , wherein the generating of the first pull-up code and the first pull-down code includes deactivating the dummy pull-down driver.

13 . The impedance calibration method of claim 11 , further comprising:
setting the dummy pull-down driver to an n−1th pull-down code; and generating an nth pull-up code and an nth pull-down code by calibrating the pull-up driver and the pull-down driver using a parallel resistance value of the external resistance and the dummy pull-down driver as the reference resistance, wherein n is an integer greater than or equal to 3.

14 . The impedance calibration method of claim 13 , wherein the parallel resistance value of the external resistance and the dummy pull-down driver corresponds to a value obtained by dividing a value of the external resistance by the n corresponding to the number of recursive calibration steps.

15 . The impedance calibration method of claim 13 , further comprising:
setting a data driver connected to a data pad of the semiconductor memory device using the nth pull-up code and the nth pull-down code corresponding to the target resistance.

16 . The impedance calibration method of claim 11 , wherein the target resistance is provided to the semiconductor memory device through a set feature command.

17 . A semiconductor memory device, comprising:
an impedance adjustment pad; an external resistance and an on-chip dummy pull-down driver connected in parallel between the impedance adjustment pad and a ground; and an impedance calibration circuit configured to: generate a pull-up code and a pull-down code corresponding to a target resistance using the external resistance and the on-chip dummy pull-down driver as a reference resistance, set the on-chip dummy pull-down driver to a pull-down code of a previous step among a plurality of steps until a pull-up code and a pull-down code corresponding to the target resistance is generated, and perform a recursive impedance calibration operation in a current step using a parallel resistance value of the external resistance and the on-chip dummy pull-down driver determined in the previous step as the reference resistance.

18 . The semiconductor memory device of claim 17 , wherein the impedance calibration circuit is configured to deactivate the on-chip dummy pull-down driver in a first step among the plurality of steps.

19 . The semiconductor memory device of claim 17 , wherein the impedance calibration circuit includes a code register configured to store a pull-up code and a pull-down code determined in each of the plurality of steps of the recursive impedance calibration operation.

20 . The semiconductor memory device of claim 19 , wherein, in a current step among the plurality of steps, the impedance calibration circuit is configured to set the on-chip dummy pull-down driver to the pull-down code stored in the code register in a previous step.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Younggyu
• Kim Tongsung
• Bae Seungjun
• Lee Seonkyoo
• Lee Taesung

Classifications

• H03K19/01721

  by means of a pull-up or down element · CPC title

• H03K19/17784

  for supply voltage · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• H03K19/0005 Primary

  Modifications of input or output impedance · CPC title