Impedance calibration circuit and memory device including the same

Patent metadata

Field	Value
Publication number	US-11115021-B2
Application number	US-202017021728-A
Country	US
Kind code	B2
Filing date	Sep 15, 2020
Priority date	Feb 5, 2020
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

First claim

What is claimed is:

1. An impedance calibration circuit comprising:
a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor;
a second code generation circuit configured to:
form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and
generate a second code by using the second reference resistor; and
a target impedance code generation circuit configured to:
generate a target impedance code based on the first code, the second code, and a target impedance value, and
form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

2. The impedance calibration circuit of claim 1 , wherein the target impedance code generation circuit is configured to:
compare the target impedance value with a threshold impedance value, and
generate the target impedance code based on a code selected from the first code and the second code according to a result of the comparing.

3. The impedance calibration circuit of claim 2 , wherein the target impedance code generation circuit is configured to:
when the target impedance value is greater than the threshold impedance value, either generate the first code as the target impedance code or generate the target impedance code by shifting the first code, and
when the target impedance value is less than the threshold impedance value, either generate the second code as the target impedance code or generate the target impedance code by shifting the second code.

4. The impedance calibration circuit of claim 1 , wherein the target impedance code generation circuit comprises:
an impedance comparator configured to output a comparison result by comparing the target impedance value with a threshold impedance value; and
an operator circuit configured to generate the target impedance code, based on a code selected from the first code and the second code according to a result of the comparing.

5. The impedance calibration circuit of claim 1 , wherein the first code generation circuit comprises:
at least one ZQ pull-up driver configured to form a first pull-up impedance, based on a first pull-up code included in the first code; and
at least one ZQ pull-down driver configured to form a first pull-down impedance, based on a first pull-down code included in the first code.

6. The impedance calibration circuit of claim 5 , wherein the second code generation circuit comprises:
a second reference resistance forming circuit configured to form a resistance of the second reference resistor, based on the first pull-up code or the first pull-down code;
at least one pull-up driver configured to form a second pull-up impedance, based on a second pull-up code included in the second code; and
at least one pull-down driver configured to form a second pull-down impedance, based on a second pull-down code included in the second code.

7. The impedance calibration circuit of claim 6 , wherein the second reference resistance forming circuit comprises a plurality of ZQ pull-up drivers connected to each other in parallel, and
each of the plurality of ZQ pull-up drivers is configured to form an impedance value that is the same as the first pull-up impedance, based on the first pull-up code.

8. The impedance calibration circuit of claim 6 , wherein the second reference resistance forming circuit comprises a plurality of ZQ pull-down drivers connected to each other in parallel, and
each of the plurality of ZQ pull-down drivers is configured to form an impedance value that is the same as the first pull-down impedance, based on the first pull-down code.

9. The impedance calibration circuit of claim 6 , wherein the target impedance code generation circuit comprises:
a pull-up decoder configured to generate a target impedance pull-up code included in the target impedance code, based on the first pull-up code, the second pull-up code, and the target impedance value; and
a pull-down decoder configured to generate a target impedance pull-down code included in the target impedance code, based on the first pull-down code, the second pull-down code, and the target impedance value.

10. The impedance calibration circuit of claim 9 , wherein the termination driver is configured to form a termination impedance, and comprises:
a termination pull-up driver configured to form a pull-up termination impedance value, based on the target impedance pull-up code; and
a termination pull-down driver configured to form a pull-down termination impedance value, based on the target impedance pull-down code.

11. The impedance calibration circuit of claim 10 , wherein the termination pull-up driver comprises a plurality of PMOS transistors having widths that are sequentially doubled, each of the plurality of PMOS transistors being driven by a bit value included in the target impedance pull-up code, and
wherein the termination pull-down driver comprises a plurality of NMOS transistors having widths that are sequentially doubled, each of the plurality of NMOS transistors being driven by a bit value included in the target impedance pull-down code.

12. An impedance calibration circuit comprising:
a first code generation circuit configured to:
generate a first code by using a first reference resistor, and
form a resistance based on the first reference resistor and the first code;
a second code generation circuit including a plurality of ZQ pull-up drivers configured to form a resistance of a second reference resistor, based on the first code, the second code generation circuit configured to generate a second code by using the second reference resistor; and
a target impedance code generation circuit configured to:
select one from among the first code and the second code according to a result of comparing a target impedance value with a threshold impedance value,
generate a target impedance code based on using the selected code, and
form an impedance having the target impedance value for a termination driver connected to the impedance calibration circuit,
wherein each ZQ pull-up driver includes either one or more PMOS transistors or one or more NMOS transistors.

13. The impedance calibration circuit of claim 12 , wherein the target impedance code generation circuit is configured to:
when the target impedance value is greater than the threshold impedance value, select the first code, and
when the target impedance value is less than the threshold impedance value, select the second code.

14. The impedance calibration circuit of claim 12 , wherein the resistance of the second reference resistor corresponds to a value obtained by dividing the resistance of the first reference resistor by the number of ZQ pull-up drivers.

15. The impedance calibration circuit of claim 12 , wherein the threshold impedance value is less than the resistance of the first reference resistor and greater than the resistance of the second reference resistor.

16. The impedance calibration circuit of claim 12 , wherein the target impedance code generation circuit is configured to:
when the target impedance value is greater than the threshold impedance value, output the first code as the target impedance code in response to the target impedance value being the same as the resistance of the first reference resistor, and generate the target impedance code by shifting the first code by one bit in response to the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Tongsung
• Jo Youngmin
• Park Jungjune
• Byun Jindo
• Shin Dongho
• Ihm Jeongdon

Classifications

• G11C7/1012 Primary

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C29/50008

  of impedance · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C2207/2254

  Calibration · CPC title