Memory device for performing calibration operation

Patent metadata

Field	Value
Publication number	US-9870808-B2
Application number	US-201615295571-A
Country	US
Kind code	B2
Filing date	Oct 17, 2016
Priority date	Dec 2, 2015
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

Provided is a memory device configured to perform a calibration operation without having a ZQ pin. The memory device includes a calibration circuit configured to generate a pull-up calibration code and a pull-down calibration code which termination of a data input/output pad for impedance matching in the data input/output pad is controlled. The calibration circuit performs a first calibration operation for trimming first and second reference resistors based on an external resistor to be connected to a pad, and a second calibration operation for generating the pull-up calibration code and the pull-down calibration code based on the trimmed second reference resistor.

First claim

What is claimed is:

1. A calibration circuit of a memory device, the calibration circuit comprising:
a first calibration circuit configured to generate a trimming code for trimming a first reference resistor, based on an external resistor to be connected to a pad of the memory device; and
a second calibration circuit configured to trim a second reference resistor in response to the trimming code, and to generate a pull-up calibration code and a pull-down calibration code based on the trimmed second reference resistor,
wherein the memory device includes a pull-up driver configured to receive the pull-up calibration code and a pull-down driver configured to receive the pull-down calibration code,
wherein the pull-up driver and the pull-down driver are connected to a data input/output pad of the memory device, and
wherein termination of the data input/output pad is controlled in response to the pull-up calibration code and the pull-down calibration code.

2. The calibration circuit of claim 1 , wherein the first reference resistor and the second reference resistor are trimmed to have a resistance value the same as that of the external resistor.

3. The calibration circuit of claim 1 , wherein the data input/output pad of the memory device is configured to be connected to outside of the memory device and the pad of the memory device is configured to be not connected to outside of the memory device.

4. The calibration circuit of claim 1 , wherein the first calibration circuit comprises:
the first reference resistor connected between the pad and a ground voltage source, and configured to have a resistance value that varies according to the trimming code;
a first comparator configured to compare a voltage of the pad to a first reference voltage, and to output a first up/down signal; and
a first counter configured to perform an up/down count operation in response to the first up/down signal, and to generate the trimming code.

5. The calibration circuit of claim 4 , wherein the first comparator is supplied by a power voltage, and
wherein the first counter is supplied by an internal power voltage generated by an internal power generator of the memory device based on the power voltage.

6. The calibration circuit of claim 4 , wherein the second calibration circuit comprises:
the second reference resistor connected between a first node and the ground voltage source, and configured to have a resistance value that varies according to the trimming code;
a pull-up calibrator connected between the first node and a second node, and configured to compare a voltage of the first node to a second reference voltage, perform an up/down count operation according to a result of the comparison, and to output the pull-up calibration code; and
a pull-down calibrator configured to compare a third reference voltage to a voltage of the second node, perform an up/down count operation according to a result of the comparison, and to output the pull-down calibration code.

7. The calibration circuit of claim 6 , wherein the pull-up calibrator comprises:
a second comparator configured to compare the voltage of the first node to the second reference voltage, and to output a second up/down signal;
a second counter configured to perform an up/down count operation in response to the second up/down signal, and to generate the pull-up calibration code;
a first pull-up driver connected between a power voltage source and the first node, and configured to have a resistance value that varies according to the pull-up calibration code; and
a second pull-up driver connected between the power voltage source and the second node, and configured to have a resistance value that varies in response to the pull-up calibration code.

8. The calibration circuit of claim 7 , wherein the pull-down calibrator comprises:
a third comparator configured to compare the third reference voltage to a voltage of the second node, and to output a third up/down signal;
a third counter configured to perform an up/down count operation in response to the third up/down signal, and to generate the pull-down calibration code; and
a first pull-down driver connected between the second node and the ground voltage source, and configured to have a resistance value that varies in response to the pull-down calibration code.

9. A memory device comprising:
a memory buffer comprising conductive terminals to perform an external interfacing function of the memory device; and
memory layers stacked on the memory buffer, electrically connected to the memory buffer via through substrate vias, and each of the memory layers comprising channels providing an interface independent from the memory buffer,
wherein the memory buffer comprises a calibration circuit configured to trim a first reference resistor and a second reference resistor based on an external resistor to be connected to a conductive terminal, and to generate a pull-up calibration code and a pull-down calibration code based on the trimmed second reference resistor, and
wherein termination of a data input/output pad (a DQ pad) of each of the channels is controlled in response to the pull-up calibration code and the pull-down calibration code.

10. The memory device of claim 9 , wherein the DQ pad is connected to an output driver including a pull-up driver configured to be controlled in response to the pull-up calibration code, and including a pull-down driver configured to be controlled in response to the pull-down calibration code, and
wherein the output driver is arranged either in each of the channels or in the memory buffer.

11. The memory device of claim 9 , wherein the calibration circuit comprises:
a first calibration circuit configured to generate a trimming code for trimming the first reference resistor, based on the external resistor and a first reference voltage; and
a second calibration circuit configured to trim the second reference resistor in response to the trimming code, to generate the pull-up calibration code based on a second reference voltage, and to generate the pull-down calibration code based on a third reference voltage.

12. The memory device of claim 11 , wherein the first calibration circuit is configured to perform a first calibration operation on the memory device in wafer form, and
wherein the second calibration circuit is configured to perform a second calibration operation on the memory device in package form.

13. The memory device of claim 11 , wherein each of the memory layers includes a first counter configured to generate the trimming code, the first counter is supplied by an internal power voltage provided by an internal power voltage generator included in the memory device.

14. The calibration circuit of claim 11 , wherein the first calibration circuit comprises:
the first reference resistor connected between the conductive terminal and a ground voltage source, and configured to have a resistance value that varies according to the trimming code;
a first comparator configured to compare a voltage of the conductive terminal to the first reference voltage, and to output a first up/down signal; and
a first counter configured to perform an up/down count operation in response to the first up/down signal, and to generate the trimming code.

15. The calibration circuit of claim 14 , wherein the second calibration circuit comprises:
the second reference resistor connected between a first node and the ground voltage source, and configured to have a resistance value that varies according to the trimming code;
a second comparator configured to compare a voltage of the first node to the second

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hyunui
• Yun Won-Joo
• Yu Hye-Seung
• Song In-Dal

Classifications

• G11C7/02 Primary

  with means for avoiding parasitic signals · CPC title

• G11C7/12 Primary

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G06F3/0673

  Single storage device · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title