On chip ZQ calibration resistor trimming

Patent metadata

Field	Value
Publication number	US-9563213-B2
Application number	US-201514966891-A
Country	US
Kind code	B2
Filing date	Dec 11, 2015
Priority date	Dec 17, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

Techniques for trimming an on chip ZQ calibration resistor are disclosed. The on chip ZQ calibration resistor alleviates the need for an external ZQ calibration resistor. The on chip ZQ calibration resistor allows for a faster ZQ calibration. The trimming of on chip ZQ calibration resistor may be used to account for process variation. A correction mechanism may be used to account for temperature variation. Some of the circuitry that is used for ZQ calibration is also used for trimming the on-chip calibration resistor. This circuitry may include operational amplifiers, current mirrors, transistors, etc. The dual use of the circuitry can eliminate offset errors in an operational amplifier. The dual use can eliminate current mirror mismatch. Therefore, the trimming accuracy may be improved. The dual use also reduces the amount of circuitry that is needed for trimming the on chip ZQ calibration resistor. Thus, transistor count and chip size is reduced.

First claim

We claim:

1. An apparatus comprising:
an on-chip calibration resistor;
a variable impedance circuit coupled to a calibration node;
circuitry configured to establish a voltage at the calibration node based on a current in the on-chip calibration resistor and a reference current when the apparatus is in a first mode;
circuitry configured to establish a voltage at the calibration node based on a current in the on-chip calibration resistor and an impedance of the variable impedance circuit when the apparatus is in a second mode;
a comparator configured to compare the voltage at the calibration node with a reference voltage when the apparatus is in the first mode and in the second mode;
circuitry configured to trim the on-chip calibration resistor based on the comparison of the voltage at the calibration node with the reference voltage when the apparatus is in the first mode; and
circuitry configured to perform a ZQ calibration based on the comparison of the voltage at the calibration node with the reference voltage when the apparatus is in the second mode.

2. The apparatus of claim 1 , wherein the circuitry configured to establish a voltage at the calibration node based on a current in the on-chip calibration resistor and a reference current when the apparatus is in the first mode comprises: first scaling circuitry configured to scale a mirrored current derived from the current in the on-chip calibration resistor by a first factor and provide the scaled current to the calibration node when the apparatus is in the first mode and trimming the on-chip calibration resistor is complete;
wherein the circuitry configured to establish a voltage at the calibration node based on a current in the on-chip calibration resistor and an impedance of the variable impedance circuit comprises: second scaling circuitry configured to scale the mirrored current derived from the current in the on-chip calibration resistor by a second factor and provide the scaled current to the calibration node when the apparatus is in the second mode and the ZQ calibration is complete.

3. The apparatus of claim 1 , wherein the circuitry configured to generate the voltage at the calibration node from the current in the on-chip calibration resistor comprises:
an operational amplifier that is used in the first mode and in the second mode.

4. The apparatus of claim 1 , wherein the circuitry configured to generate the voltage at the calibration node from the current in the on-chip calibration resistor comprises:
a current mirror that is used in the first mode and in the second mode.

5. The apparatus of claim 1 , wherein the on-chip calibration resistor comprises:
an input configured to receive a trim code;
a plurality of resistors; and
a plurality of transistors that are controlled by the trim code, wherein the transistors include or exclude the resistors based on the trim code to trim the on-chip calibration resistor.

6. The apparatus of claim 5 , wherein the circuitry configured to trim the on-chip calibration resistor is configured to determine the trim code, wherein the apparatus is configured to provide the trim code to the on-chip calibration resistor while performing the ZQ calibration.

7. The apparatus of claim 5 , wherein the on-chip calibration resistor further comprises:
an input configured to receive a temperature code that is based on a present temperature;
at least one additional resistor; and
at least one additional transistor, wherein the at least one additional transistor is controlled by the temperature code to include or exclude the at least one additional resistor to change the resistance of on-chip calibration resistor to account for temperature variation.

8. The apparatus of claim 1 , further comprising:
a three-dimensional memory array comprising a plurality of non-volatile storage elements.

9. A non-volatile storage device comprising:
a plurality of non-volatile storage elements;
an on-chip calibration resistor having a first node and a second node;
a variable impedance circuit coupled to a calibration node, wherein the variable impedance circuit has an input configured to receive a ZQ impedance code, wherein the variable impedance circuit is configured to alter its impedance based on the ZQ impedance code;
reference voltage circuitry configured to provide a first reference voltage between the first node and the second node of the on-chip calibration resistor to create a current through the on-chip calibration resistor;
current generation circuitry configured to generate a second current based on the current through the on-chip calibration resistor;
calibration voltage providing circuitry configured to provide a calibration voltage to the calibration node based on the second current and the impedance of the variable impedance circuit and to provide a calibration voltage to the calibration node based on the second current and a reference current;
ZQ calibration circuitry configured to perform a ZQ calibration based on a comparison of the calibration voltage and a second reference voltage; and
on-chip resistor calibration circuitry configured to trim the on-chip calibration resistor based on a comparison of the calibration voltage and the second reference voltage.

10. The non-volatile storage device of claim 9 , wherein the circuitry configured to perform the ZQ calibration comprises a comparator configured to compare the second reference voltage with the calibration voltage when the ZQ calibration is performed, wherein the comparator is configured to compare the second reference voltage with the calibration voltage when the on-chip calibration resistor is trimmed.

11. The non-volatile storage device of claim 9 , wherein the circuitry configured to provide the first reference voltage between the first node and the second node of the on-chip calibration resistor comprises an operational amplifier configured to provide the first reference voltage when the ZQ calibration is performed and also when the on-chip calibration resistor is trimmed.

12. The non-volatile storage device of claim 9 , wherein the circuitry configured to generate the second current comprises an operational amplifier configured to provide the first reference voltage to a node that provides the second current when the ZQ calibration is performed and also when the on-chip calibration resistor is trimmed.

13. The non-volatile storage device of claim 9 , wherein the circuitry configured to generate the second current comprises a current mirror that is used to generate the second current when the ZQ calibration is performed and also when the on-chip calibration resistor is trimmed.

14. The non-volatile storage device of claim 9 , wherein the circuitry configured to provide the calibration voltage to the calibration node based on the second current comprises:
first scaling circuitry configured to scale the second current by a first factor when trimming the on-chip calibration resistor is complete; and
second scaling circuitry configured to scale the second current by a second factor when performing the ZQ calibration is complete.

15. The non-volatile storage device of claim 9 , wherein the on-chip calibration resistor comprises:
an input configured to receive a trim code; and
a plurality of resistor legs in parallel, each of the resistor legs comprising a resistor, at least some of the resistor legs comprising a selection transistor in series with the resistor of that leg, wherein the selection transistors are configured to be controlled by the trim code to select resistors in the plurality of resistor legs.

16. A method comp

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Addepalli Sravanti
• Yadala Sridhar

Classifications

• H03K19/0005

  Modifications of input or output impedance · CPC title

• G05F1/463 Primary

  Sources providing an output which depends on temperature · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title