Impedance calibration circuit

Patent metadata

Field	Value
Publication number	US-11283447-B2
Application number	US-202117235873-A
Country	US
Kind code	B2
Filing date	Apr 20, 2021
Priority date	May 25, 2020
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

An impedance calibration circuit includes first and second calibration circuits, a switch circuit and a control circuit. The first calibration circuit is coupled to an external resistance, and generates a first voltage. The second calibration circuit generates second and third voltages. The switch circuit is coupled to the first and second calibration circuits. The switch circuit selectively provides the first, second, and third voltages to first and second nodes. The control circuit is coupled to the first and second nodes. The control circuit generates first, second, and third control signals according to voltages of the first and second nodes. In a first time interval, the switch circuit provides the first voltage to the first and second nodes. In a second time interval, the switch circuit provides the second voltage to the first and second nodes, or provides the second and third voltages respectively to the first and second nodes.

First claim

What is claimed is:

1. An impedance calibration circuit, comprising:
a first calibration circuit adapted to be coupled to an external resistance through a pad and generating a first voltage according to a first control signal;
a second calibration circuit generating a second voltage and a third voltage according to the first control signal, a second control signal, and a third control signal;
a switch circuit coupled to the first calibration circuit and the second calibration circuit, wherein the switch circuit selectively provides the first voltage, the second voltage, and the third voltage to a first node and a second node; and
a control circuit coupled to the switch circuit at the first node and the second node, wherein the control circuit performs comparisons of voltages of the first node and the second node respectively with a first reference signal and a second reference signal, and generates the first control signal, the second control signal, and the third control signal according to comparison results,
wherein in a first time interval, the switch circuit provides the first voltage to the first node and the second node, and
wherein in a second time interval, the switch circuit provides the second voltage to the first node and the second node, or provides the second voltage and the third voltage respectively to the first node and the second node.

2. The impedance calibration circuit according to claim 1 , wherein the switch circuit first provides the first voltage to the first node and the second node, so that the control circuit compares the first voltage with voltages of the first reference signal and the second reference signal to generate the first control signal, and then provides the second voltage to the first node and the second node, so that the control circuit compares the second voltage with the voltages of the first reference signal and the second reference signal to generate the second control signal and the third control signal.

3. The impedance calibration circuit according to claim 1 , wherein the switch circuit first provides the first voltage to the first node and the second node, so that the control circuit compares the first voltage with voltages of the first reference signal and the second reference signal to generate the first control signal, and then provides the second voltage and the third voltage to the first node and the second node, so that the control circuit compares the second voltage and the third voltage respectively with the voltages of the first reference signal and the second reference signal to generate the second control signal and the third control signal.

4. The impedance calibration circuit according to claim 1 , wherein the first calibration circuit comprises a first transistor, wherein a first terminal of the first transistor receives an operating voltage, a second terminal of the first transistor is coupled to the pad, and a control terminal of the first transistor receives the first control signal to adjust an impedance value of the first transistor and generate the first voltage at the second terminal of the first transistor.

5. The impedance calibration circuit according to claim 1 , wherein the second calibration circuit comprises:
a first bias circuit comprising a first transistor and a second transistor, wherein a first terminal of the first transistor receives an operating voltage, a second terminal of the first transistor is coupled to a first terminal of the second transistor, a second terminal of the second transistor receives a ground voltage, and control terminals of the first transistor and the second transistor respectively receive the first control signal and a first sub-control signal of the second control signal; and
a second bias circuit comprising a third transistor and a fourth transistor, wherein a first terminal of the third transistor receives the operating voltage, a second terminal of the third transistor is coupled to a first terminal of the fourth transistor, a second terminal of the fourth transistor receives the ground voltage, and control terminals of the third transistor and the fourth transistor respectively receive the first control signal and a second sub-control signal of the second control signal,
wherein the first bias circuit generates the second voltage at the second terminal of the first transistor, and the second bias circuit generates the third voltage at the second terminal of the third transistor.

6. The impedance calibration circuit according to claim 5 , wherein the switch circuit comprises:
a first switch, wherein a first terminal of the first switch is coupled to the pad to receive the first voltage, and a second terminal of the first switch is coupled to the first node;
a second switch, wherein a first terminal of the second switch is coupled to the first bias circuit to receive the second voltage, and a second terminal of the second switch is coupled to the first node;
a third switch, wherein a first terminal of the third switch is coupled to the second bias circuit to receive the third voltage, and a second terminal of the third switch is coupled to the second node; and
a fourth switch, wherein a first terminal of the fourth switch is coupled to the first node, and a second terminal of the fourth switch is coupled to the second node.

7. The impedance calibration circuit according to claim 6 , wherein when the switch circuit provides the first voltage to the first node and the second node, the first switch and the fourth switch are turned on, and the second switch and the third switch are turned off.

8. The impedance calibration circuit according to claim 6 , wherein when the switch circuit provides the second voltage to the first node and the second node, the first switch and the third switch are turned off, and the second switch and the fourth switch are turned on.

9. The impedance calibration circuit according to claim 6 , wherein when the switch circuit provides the second voltage and the third voltage respectively to the first node and the second node, the first switch and the fourth switch are turned off, and the second switch and the third switch are turned on.

10. The impedance calibration circuit according to claim 6 , wherein the control circuit comprises:
a first comparator, wherein a first input terminal of the first comparator is coupled to the first node, and a second input terminal of the first comparator receives the first reference signal to generate a comparison result at an output terminal of the first comparator;
a second comparator, wherein a first input terminal of the second comparator is coupled to the second node, and a second input terminal of the second comparator receives the second reference signal to generate a comparison result at an output terminal of the second comparator; and
an operating circuit coupled to the output terminals of the first comparator and the second comparator to generate the first control signal and the second control signal according to the comparison results of the first comparator and the second comparator.

11. The impedance calibration circuit according to claim 10 , wherein the second calibration circuit further generates a fourth voltage according to a fourth control signal, and the second calibration circuit further comprises:
a third bias circuit comprising a fifth transistor and a sixth transistor, wherein a first terminal of the fifth transistor receives the operating voltage, a second terminal of the fifth transistor is coupled to a first terminal of the sixth transistor, a second terminal of the sixth transistor receives the ground voltage, and control terminals of the fifth transistor and the sixth transistor respectively receive

Assignees

• Winbond Electronics Corp

Inventors

• Michioka Yoshihisa

Classifications

• G11C29/16

  using microprogrammed units, e.g. state machines · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G11C29/12005

  comprising voltage or current generators · CPC title

• G11C29/14

  Implementation of control logic, e.g. test mode decoders · CPC title

• G11C29/1201

  comprising I/O circuitry · CPC title