Impedance calibration circuit and semiconductor memory apparatus having the same

Patent metadata

Field	Value
Publication number	US-10020808-B2
Application number	US-201615200064-A
Country	US
Kind code	B2
Filing date	Jul 1, 2016
Priority date	Apr 14, 2016
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

An impedance calibration circuit includes a first reference resistor electrically coupled to a calibration pad, a second reference resistor which is coupled to the first reference resistor in parallel and a resistance value of the second reference resistor is varied according to an operation voltage mode, and a calibration circuit electrically coupled to the calibration pad and configured to generate a calibration code according to a resistance value formed by the first reference resistor and the second reference resistor and calibrate an impedance value in the calibration pad according to the calibration code.

First claim

What is claimed is:

1. A circuit for calibrating impedance, the circuit comprising:
a first reference resistor electrically coupled to a calibration pad;
a second reference resistor which is coupled to the first reference resistor in parallel and a resistance value of the second reference resistor is varied according to an operation voltage mode; and
a calibration circuit electrically coupled to the calibration pad and configured to generate a calibration code according to a resistance value formed by the first reference resistor and the second reference resistor and calibrate an impedance value in the calibration pad according to the calibration code.

2. The circuit of claim 1 , wherein the first reference resistor and the second reference resistor are embedded in a semiconductor chip.

3. The circuit of claim 1 , wherein the first reference resistor is disposed outside a semiconductor chip, and the second reference resistor is embedded in the semiconductor chip.

4. The circuit of claim 1 , wherein a resistance value of the second reference resistor is determined in response to a control signal generated according to the operation voltage mode.

5. The circuit of claim 1 , wherein only the first reference resistor operates as a reference resistor in a first operation voltage mode, and the first reference resistor and the second reference resistor operate as the reference resistor in a second operation voltage mode.

6. The circuit of claim 5 , wherein the circuit operates at a first voltage level in the first operation voltage mode, and the circuit operates at a second voltage level in the second operation voltage mode.

7. The circuit of claim 1 , wherein the calibration circuit further comprises a first pull-up circuit, a second pull-up circuit, and a pull-down circuit,
and when a calibration operation is completed a reference resistor has a same impedance value as the first pull-up circuit and the second pull-up circuit has a same impedance value as the pull-down circuit.

8. The circuit of claim 1 , further comprising a reference voltage generation circuit configured to divide a power voltage to generate a plurality of divided voltages and output one of the divided voltages as a reference voltage.

9. A semiconductor memory apparatus comprising:
an impedance calibration circuit configured to generate a calibration code according to a resistance value formed by a first reference resistor and a second reference resistor of which a resistance value is varied according to an operation voltage mode and calibrate an impedance value in a calibration pad to which the first and second reference resistors are coupled in response to the calibration code; and
a data input/output driver configured to calibrate an impedance value of an output signal in response to the calibration code.

10. The semiconductor memory apparatus of claim 9 , wherein the first reference resistor and the second reference resistor are embedded in the semiconductor memory apparatus.

11. The semiconductor memory apparatus of claim 9 , wherein the first reference resistor is disposed outside the semiconductor memory apparatus, and the second reference resistor is embedded in the semiconductor memory apparatus.

12. The semiconductor memory apparatus of claim 9 , wherein a resistance value of the second reference resistor is determined in response to a control signal generated according to the operation voltage mode.

13. The semiconductor memory apparatus of claim 9 , wherein the data input/output driver is configured to receive input data and generate output data by driving the input data according to the calibration code.

14. The semiconductor memory apparatus of claim 13 , wherein the data input/out driver further comprises:
a pre pull-up driver configured to generated a pull-up control signal in response to receiving a first code provided by the impedance calibration circuit and the input data,
a pre pull-down driver configured to generate a pull-down control signal in response to receiving a second code provided by the impedance calibration circuit and the input data, and
a main pull-up driver and a main pull-down driver configured generate the output signal in response to the pull-up control signal and the pull-down control signal.

15. The semiconductor memory apparatus of claim 14 , wherein the impedance value of the output signal is calibrated in response to the pull-up control signal and the pull-down control signal.

16. The semiconductor memory apparatus of claim 14 , wherein the main pull-up driver further comprises a plurality of legs driven by a pull-up control signal.

17. The semiconductor memory apparatus of claim 14 , wherein the main pull-up driver is comprised of a plurality of legs, where the plurality of legs includes a first group of legs comprised of at least one leg having a first resistance value, a second group of legs comprised of at least one leg having a second resistance value, and a third group of legs comprised of at least one leg having a third resistance value.

18. The semiconductor memory apparatus of claim 14 , wherein the main pull-up driver is comprised of a plurality of legs divided into a plurality of groups of legs and the pull-up control signal is comprised of a plurality of bits, wherein each group of legs is controlled by at least one bit of the pull-up control signal, where no bit is used to control more than one group of legs.

19. The semiconductor apparatus of claim 9 , wherein the impedance value is determined according to more than one calibration code.

Assignees

• Sk Hynix Inc

Inventors

• Jang Dong Wook

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• H03K19/0005 Primary

  Modifications of input or output impedance · CPC title

• G11C29/025

  in signal lines · CPC title