Variable resistance memory device and electronic device including the same

Patent metadata

Field	Value
Publication number	US-12477748-B2
Application number	US-202318299403-A
Country	US
Kind code	B2
Filing date	Apr 12, 2023
Priority date	Aug 19, 2022
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

Provided area a variable resistance memory device and/or an electronic device including the same. The variable resistance memory device includes: a resistance change layer including a metal oxide having an oxygen deficient ratio greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.

First claim

What is claimed is:

1 . A variable resistance memory device comprising:
a resistance change layer comprising a metal oxide that includes a first metal element and a second metal element, the metal oxide having an oxygen deficient ratio greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.

2 . The variable resistance memory device of claim 1 , wherein a content of the first metal element with respect to an entire metal of the resistance change layer is greater than or equal to about 50 at %.

3 . The variable resistance memory device of claim 1 , wherein a content of the second metal element with respect to an entire metal of the resistance change layer is less than or equal to about 35 at %.

4 . The variable resistance memory device of claim 1 , wherein the first metal element comprises at least one of Ta, Ti, Sn, Cr, and Mn.

5 . The variable resistance memory device of claim 1 , wherein the second metal element comprises at least one of Hf, Al, Nb, La, Zr, Sc, W, V, and Mo.

6 . The variable resistance memory device of claim 1 , wherein the resistance change layer further comprises Si.

7 . The variable resistance memory device of claim 1 , wherein the semiconductor layer is configured to receive a write voltage having an absolute value less than or equal to about 4V is applied thereto.

8 . The variable resistance memory device of claim 1 , further comprising:
an oxide layer between the semiconductor layer and the resistance change layer.

9 . The variable resistance memory device of claim 8 , wherein a thickness of the oxide layer is less than a thickness of the resistance change layer.

10 . The variable resistance memory device of claim 1 , wherein
the resistance change layer comprises a first resistance change layer and a second resistance change layer sequentially arranged in a direction away from the semiconductor layer; and an oxygen deficient ratio of the first resistance change layer is greater than an oxygen deficient ratio of the second resistance change layer.

11 . The variable resistance memory device of claim 1 , wherein
at least three of the plurality of gate electrodes are arranged periodically, and a pitch of the at least three of the plurality of gate electrodes is less than or equal to about 20 nm.

12 . The variable resistance memory device of claim 1 , further comprising:
a pillar, wherein the resistance change layer, the semiconductor layer, and the gate insulating layer sequentially surround the pillar in a shell shape, and the plurality of gate electrodes and an insulating element surround the gate insulating layer in a shell shape.

13 . The variable resistance memory device of claim 12 , wherein the pillar comprises an insulating material.

14 . The variable resistance memory device of claim 12 , wherein the pillar comprises a conductive material.

15 . The variable resistance memory device of claim 14 , wherein the pillar is configured to receive a voltage that is greater than or equal to a voltage applied to the semiconductor layer.

16 . A variable resistance memory device comprising:
a resistance change layer comprising silicon and comprising a metal oxide having an oxygen deficient ratio that is greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.

17 . The variable resistance memory device of claim 16 , wherein the resistance change layer comprises at least one of Ta, Ti, Sn, Cr, and Mn.

18 . The variable resistance memory device of claim 16 , wherein a content of silicon with respect to a sum of metals and silicon of the resistance change layer is less than or equal to about 35 at %.

19 . A variable resistance memory device comprising:
a resistance change layer comprising a first metal oxide having an oxygen deficient ratio that is greater than or equal to about 9% and a second metal oxide having an oxygen deficient ratio that is less than 9%, wherein a content of the first metal oxide is greater than a content of the second metal oxide; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of gate electrodes on the gate insulating layer to be apart from each other.

20 . The variable resistance memory device of claim 19 , wherein a content of a metal included in the second metal oxide with respect to entire metal included in the resistance change layer is less than or equal to about 35 at %.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Seyun
• Kang Jooheon
• Kim Sunho
• Kim Yumin
• Park Garam
• Song Hyunjae
• Ahn Dongho
• Yang Seungyeul
• Woo Myunghun
• Lee Jinwoo

Classifications

• H10B63/34

  of the vertical channel field-effect transistor type · CPC title

• H10N70/8265

  on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices · CPC title

• H10B63/845 Primary

  the switching components being connected to a common vertical conductor · CPC title

• H10N70/24

  based on migration or redistribution of ionic species, e.g. anions, vacancies · CPC title

• H10B63/84

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title