Semiconductor memory device including variable resistance element

Patent metadata

Field	Value
Publication number	US-9966136-B2
Application number	US-201715443084-A
Country	US
Kind code	B2
Filing date	Feb 27, 2017
Priority date	Sep 9, 2016
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

According to one embodiment, a variable resistance memory includes first to third insulating layers, first and second variable resistance layers, first and second semiconductor layers, and first and second electric conductors. The first insulating layer extends in a first direction. The first and second electric conductors are in contact with the second and third insulating layers respectively. The first to third insulating layers, the first and second variable resistance layers and the first and second semiconductor layers are disposed between the first and second electric conductors in a second direction different from the first direction.

First claim

The invention claimed is:

1. A variable resistance memory comprising:
a first insulating layer extending in a first direction;
first and second variable resistance layers, the first insulating layer being disposed between the first and second variable resistance layers in a second direction different from the first direction;
first and second semiconductor layers, the first insulating layer and the first and second variable resistance layers being disposed between the first and second semiconductor layers in the second direction;
second and third insulating layers, the first insulating layer, the first and second variable resistance layers and the first and second semiconductor layers being disposed between the second and third insulating layers in the second direction;
first and second electric conductors provided in a first layer, the first and second electric conductors being in contact with the second and third insulating layers respectively, the first to third insulating layers, the first and second variable resistance layers and the first and second semiconductor layers being disposed between the first and second electric conductors in the second direction;
third and fourth electric conductors provided in a second layer different from the first layer, the third and fourth electric conductors being in contact with the second and third insulating layers respectively, the first to third insulating layers and the first and second semiconductor layers being disposed between the third and fourth electric conductors in the second direction;
a fifth electric conductor being in contact with one ends of the first and second semiconductor layers in the first direction;
a sixth electric conductor that extends in a third direction different from the first direction, and is in contact with the fifth electric conductor, the fifth electric conductor being disposed between the one ends of the first and second semiconductor layers and the sixth electric conductor;
a seventh electric conductor being in contact with the other ends of the first and second semiconductor layers in the first direction;
an eighth electric conductor that extends in a fourth direction different from the first to third directions, and is in contact with the seventh electric conductor, the seventh electric conductor being disposed between the other ends of the first and second semiconductor layers and the eighth electric conductor,
a first memory cell that is disposed between the first and second electric conductors, and includes part of the first variable resistance layer; and
a second memory cell that is disposed between the first and second electric conductors, and includes part of the second variable resistance layer,
wherein no variable resistance layer is provided in a region between the third and fourth electric conductors,
wherein the fifth electric conductor has a rectifying function between the sixth electric conductor and the first and second semiconductor layers,
wherein the first and second variable resistance layers each take a high resistance state or a low resistance state, and
in a read operation of the first memory cell,
a first voltage is applied to the first and second electric conductors, a second voltage higher than the first voltage is applied to the third electric conductor, a third voltage lower than the second voltage is applied to the fourth electric conductor, a fourth voltage is applied to the sixth electric conductor, and a fifth voltage different from the fourth voltage is applied to the eighth electric conductor.

2. The memory of claim 1 , wherein
the first to fourth electric conductors extend in the fourth direction.

3. The memory of claim 1 , further comprising:
ninth and tenth electric conductors provided in a third layer between the first and second layers, the ninth and tenth electric conductors being in contact with the second and third insulating layers respectively, the first to third insulating layers, the first and second variable resistance layers and the first and second semiconductor layers being disposed between the ninth and tenth electric conductors in the second direction, wherein
a sixth voltage higher than the first voltage is applied to the ninth and tenth electric conductors in the read operation of the first memory cell.

4. The memory of claim 1 , further comprising:
a fourth insulating layer extending in the first direction;
third and fourth variable resistance layers, the fourth insulating layer being disposed between the third and fourth variable resistance layers in the second direction;
third and fourth semiconductor layers, the fourth insulating layer and the third and fourth variable resistance layers being disposed between the third and fourth semiconductor layers in the second direction;
fifth and sixth insulating layers, the fourth insulating layer, the third and fourth variable resistance layers and the third and fourth semiconductor layers being disposed between the fifth and sixth insulating layers in the second direction, the fifth insulating layer being in contact with the first and third electric conductors;
a ninth electric conductor provided in the first layer, the ninth electric conductor being in contact with the sixth insulating layer, the fourth to sixth insulating layers, the third and fourth variable resistance layers and the third and fourth semiconductor layers being disposed between the first and ninth electric conductors in the second direction;
a tenth electric conductor provided in the second layer, the tenth electric conductor being in contact with the sixth insulating layer, the fourth to sixth insulating layers and the third and fourth semiconductor layers being disposed between the third and tenth electric conductors in the second direction;
an eleventh electric conductor being in contact with one ends of the third and fourth semiconductor layers in the first direction, the eleventh electric conductor being disposed between the one ends of the third and fourth semiconductor layers and the sixth electric conductor;
a twelfth electric conductor being in contact with the other ends of the third and fourth semiconductor layers in the first direction; and
a thirteenth electric conductor that extends in the fourth direction, and is in contact with the twelfth electric conductor, the twelfth electric conductor being disposed between the other ends of the third and fourth semiconductor layers and the thirteenth electric conductor, wherein
no variable resistance layer is provided in a region between the third and tenth electric conductors, and
the eleventh electric conductor has a rectifying function between the sixth electric conductor and the third and fourth semiconductor layers.

5. The memory of claim 4 , further comprising:
a first memory cell that is disposed between the first and second electric conductors, and includes part of the first variable resistance layer; and
a second memory cell that is disposed between the first and second electric conductors, and includes part of the second variable resistance layer, wherein
the first and second variable resistance layers each take a high resistance state or a low resistance state, and
in a read operation of the first memory cell,
a first voltage is applied to the first, second, and ninth electric conductors, a second voltage higher than the first voltage is applied to the third electric conductor, a third voltage lower than the second voltage is applied to the fourth and tenth electric conductors, a fourth voltage is applied to the sixth electric conductor, and a fifth voltage different from the fourth voltage is applied to the eighth electric conductor.

6. The memory of claim 1 , wherein
the first and second variable resistance layers contain germanium, antimony,

Assignees

• Toshiba Memory Corp

Inventors

• Ogiwara Ryu
• Takashima Daisaburo

Classifications

• H01L27/2436

  Electricity · mapped topic

• H01L45/12

  Electricity · mapped topic

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C2213/74

  Array wherein each memory cell has more than one access device · CPC title