Non-volatile memory device and operation method thereof

Patent metadata

Field	Value
Publication number	US-10903235-B2
Application number	US-201916662299-A
Country	US
Kind code	B2
Filing date	Oct 24, 2019
Priority date	Nov 15, 2018
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

Provided is a non-volatile memory device including a control logic, a semiconductor layer, a resistance switching layer, a gate oxide layer, and a gate stack including a plurality of gates and a plurality of insulating layers, wherein the plurality of gates and the plurality of insulating layers are stacked alternately with each other. The resistance switching layer is provided between the semiconductor layer and the gate stack. The gate oxide layer is provided between the resistance switching layer and the gate stack. A cell string including a plurality of memory cells is formed by the gate stack, the resistance switching layer, and the gate oxide layer.

First claim

What is claimed is:

1. A non-volatile memory device comprising:
a control logic;
a semiconductor layer extending in a first direction;
a gate stack including a plurality of gates and a plurality of insulating layers, both extending in a second direction different than the first direction, and the plurality of gates and the plurality of insulating layers being stacked alternately with each other;
a resistance switching layer extending in the first direction between the gate stack and the semiconductor layer; and
a gate oxide layer extending in the first direction between the gate stack and the resistance switching layer,
wherein a cell string is formed by the gate stack, the resistance switching layer, and the gate oxide layer.

2. The non-volatile memory device of claim 1 , wherein
the cell string comprises a selected memory cell and a non-selected memory cell, and
the control logic is configured to perform a program operation with respect to the selected memory cell by,
applying a first positive voltage to a string selection line connected to the selected memory cell,
grounding a bit line connected to the selected memory cell,
applying a second positive voltage that is greater than the first positive voltage to a word line connected to the selected memory cell, and
applying the first positive voltage to a word line connected to the non-selected memory cell.

3. The non-volatile memory device of claim 1 , wherein
the cell string comprises a selected memory cell and a non-selected memory cell, and
the control logic is configured to perform an erase operation with respect to the selected memory cell by,
applying a first positive voltage to a string selection line connected to the selected memory cell, ground a bit line connected to the selected memory cell,
applying a negative voltage having an absolute value that is greater than an absolute value of the first positive voltage to a word line connected to the selected memory cell, and
applying the first positive voltage to a word line connected to the non-selected memory cell.

4. The non-volatile memory device of claim 2 , wherein
the control logic is further configured to, based on the bit line connected to the selected memory cell being grounded,
cause the first positive voltage to be applied to the word line connected to the non-selected memory cell, and
cause the second positive voltage to be applied to the word line connected to the selected memory cell, a ground channel is formed in the semiconductor layer, and
the selected memory cell is configured such that, based on a voltage difference between a gate corresponding to the selected memory cell and the ground channel based on the second positive voltage to the word line connected to the selected memory cell, oxygen vacancies in the selected memory cell move towards the semiconductor layer such that the program operation with respect to the selected memory cell is performed.

5. The non-volatile memory device of claim 3 , wherein
the control logic is further configured to, based on the bit line connected to the selected memory cell being grounded,
cause the first positive voltage to be applied to the word line connected to the non-selected memory cell, and
cause the negative voltage to be applied to the word line connected to the selected memory cell to form a ground channel in the semiconductor layer due to a fringing field effect caused by the non-selected memory cell that is adjacent to the selected memory cell, and
the memory cell is configured such that, based on a voltage difference between a gate corresponding to the selected memory cell and the ground channel and the negative voltage to the word line connected to the selected memory cell, oxygen vacancies in the selected memory cell move in a direction opposite to the semiconductor layer such that the erase operation with respect to the selected memory cell is performed.

6. The non-volatile memory device of claim 1 , wherein
the cell string includes a selected memory cell and a non-selected memory cell, and
the control logic is configured to perform a read operation with respect to the selected memory cell by,
applying a first positive voltage to a string selection line connected to the selected memory cell,
applying a read voltage to a bit line connected to the selected memory cell,
applying a voltage having an absolute value that is less than an absolute value of the first positive voltage to a word line connected to the selected memory cell, and
applying the first positive voltage to a word line connected to the non-selected memory cell.

7. The non-volatile memory device of claim 6 , wherein
the memory cell is further configured such that a resistance state of the selected memory cell is based on positions of oxygen vacancies in the selected memory cell, and
the control logic is further configured to apply the read voltage to the bit line connected to the selected memory cell and read data based on a read current that is determined by the resistance state of the selected memory cell.

8. The non-volatile memory device of claim 7 , wherein
the selected memory cell is configured to enter a low resistance state as the oxygen vacancies in the selected memory cell move towards the semiconductor layer based on a program operation being performed with respect to the selected memory cell, and
the selected memory cell is configured to enter a high resistance state as the oxygen vacancies in the selected memory cell move in a direction opposite to the semiconductor layer based on an erase operation being performed with respect to the selected memory cell.

9. The non-volatile memory device of claim 1 , wherein
a word plane comprises a plurality of selected memory cells that are connected to a word line, and
the control logic is further configured to perform an erase operation with respect to the plurality of selected memory cells by,
applying a first positive voltage to a plurality of string selection lines connected to the plurality of selected memory cell,
grounding a bit line connected to the plurality of selected memory cells,
applying a negative voltage having an absolute value that is greater than an absolute value of the first positive voltage to the word line, and
applying the first positive voltage to a word line other than the word line.

10. The non-volatile memory device of claim 1 , wherein
the gate, the semiconductor, and the gate oxide layer form a transistor, and
the control logic is further configured to perform a read operation by causing a memory cell included in the cell string corresponding to a circuit in which the transistor and a resistor corresponding to the resistance switching layer to be connected in parallel.

11. The non-volatile memory device of claim 10 , wherein
the cell string comprises a selected memory cell and a non-selected memory cell, and
the control logic is further configured to, based on the control logic performing the read operation,
cause a transistor corresponding to the selected memory cell to be turned off based on a voltage of a word line connected to the selected memory cell, and
cause a transistor corresponding to the non-selected memory cell to be turned on based on a second positive voltage having an absolute value that is greater than an absolute value of the voltage of the word line connected to the non-selected memory cell.

12. The non-volatile memory device of claim 10 , wherein
the cell string comprises a plurality of memory cells, and
the control logic is further configured to perform a program operation or an erase operation by,
causing a bit line connected to the plurality of memory cells to

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Jungho
• Mizusaki Soichiro
• Cho Youngjin

Classifications

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D44/456

  Structures for regeneration, refreshing or leakage compensation · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title