3D non-volatile memory array utilizing metal ion source

Patent metadata

Field	Value
Publication number	US-9947685-B2
Application number	US-201615264919-A
Country	US
Kind code	B2
Filing date	Sep 14, 2016
Priority date	Mar 16, 2016
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

According to one embodiment, a semiconductor memory device includes a semiconductor layer, a plurality of conductive layers, a plurality of insulating layers, an intermediate layer, and a controller. The conductive layers and the insulating layers are alternately provided. The intermediate layer is provided between the plurality of conductive layers and the semiconductor layer. The controller is configured to perform first and second operations. In first operation, the controller applies a first voltage to the semiconductor layer, applies a second voltage higher than the first voltage to a first conductive layer, and applies a third voltage to other conductive layers. In the second operation, the controller applies a fourth voltage to the semiconductor layer, applies a fifth voltage to the first conductive layer, and applies a sixth voltage to the other conductive layers.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a semiconductor layer extending in a first direction and including a first end portion and a second end portion;
a plurality of conductive layers and a plurality of insulating layers alternately provided along the first direction;
an intermediate layer provided between the plurality of conductive layers and the semiconductor layer; and
a controller electrically connected with the plurality of conductive layers and the semiconductor layer,
the controller being configured to perform a first operation and a second operation,
in the first operation, the controller applying a first voltage to the semiconductor layer, applying a second voltage higher than the first voltage to a first conductive layer included in the plurality of conductive layers, and applying a third voltage between the first voltage and the second voltage to other conductive layers included in the plurality of conductive layers, and
in the second operation, the controller applying a fourth voltage to the semiconductor layer, applying a fifth voltage lower than the fourth voltage to the first conductive layer, and applying a sixth voltage to the other conductive layers, the fourth voltage being between the fifth voltage and the sixth voltage,

a first electrical resistance between the first end portion and the second end portion in a first state after the first operation being lower than a second electrical resistance between the first end portion and the second end portion in a second state after the second operation,
the first electrical resistance including an electrical resistance of a current path along the first direction, the current path including a region of the intermediate layer, the region including metallic elements.

2. The device according to claim 1 , wherein
the controller further performs a third operation in which the controller applies a seventh voltage to the first end portion, applies an eighth voltage higher than the seventh voltage to the second end portion, applies a ninth voltage to the first conductive layer, and applies a tenth voltage to the other conductive layers,
an absolute value of a difference between the ninth voltage and the seventh voltage is smaller than an absolute value of a difference between the second voltage and the first voltage, and
an absolute value of a difference between the tenth voltage and the seventh voltage is smaller than the absolute value of the difference between the second voltage and the first voltage.

3. The device according to claim 1 , wherein
the plurality of conductive layers contain a metallic element of at least one of copper or silver, and
the intermediate layer contains at least one of SiO x , SiON, AlO x , TaO x , TiO x , ZrO x , GdO x , or HfO x .

4. The device according to claim 3 , wherein
the intermediate layer includes a first region between the first conductive layer and the semiconductor layer, and
a concentration of the metallic element in the first region in the first state is higher than a concentration of the metallic element in the first region in the second state.

5. The device according to claim 3 , wherein
the intermediate layer includes a first region between the first conductive layer and the semiconductor layer,
the first region includes a conductive layer-side region and a semiconductor layer-side region provided between the conductive layer-side region and the semiconductor layer, and
a concentration of the metallic element in the semiconductor layer-side region in the first state is higher than a concentration of the metallic element in the conductive layer-side region in the first state.

6. The device according to claim 1 , wherein
the intermediate layer contains silicon, oxygen, and nitrogen,
the intermediate layer includes a conductive layer-side region and a semiconductor layer-side region provided between the conductive layer-side region and the semiconductor layer, and
a concentration of nitrogen in the semiconductor layer-side region is lower than a concentration of nitrogen in the conductive layer-side region.

7. The device according to claim 1 , wherein
the intermediate layer contains an anatase-type titanium oxide, and
the semiconductor layer contains silicon.

8. The device according to claim 7 , wherein
the intermediate layer includes a first region between the first conductive layer and the semiconductor layer,
the first region includes a conductive layer-side region and a semiconductor layer-side region provided between the conductive layer-side region and the semiconductor layer, and
a concentration of oxygen in the semiconductor layer-side region in the first state is lower than a concentration of oxygen in the semiconductor layer-side region in the second state.

9. The device according to claim 7 , wherein
the intermediate layer includes a first region between the first conductive layer and the semiconductor layer,
the first region includes a conductive layer-side region and a semiconductor layer-side region provided between the conductive layer-side region and the semiconductor layer, and
a concentration of oxygen in the semiconductor layer-side region in the first state is lower than a concentration of oxygen in the conductive layer-side region in the first state.

10. The device according to claim 1 , wherein
the semiconductor layer extends in a stacked member including the plurality of conductive layers and the plurality of insulating layers in the first direction.

11. The device according to claim 7 , wherein
the intermediate layer includes a conductive layer-side region and a semiconductor layer-side region provided between the conductive layer-side region and the semiconductor layer,
the intermediate layer includes a first region between the first conductive layer and the semiconductor layer, and
a concentration of oxygen in the semiconductor layer-side region of the first region in the first state is lower than a concentration of oxygen of the first region in the second state.

12. The device according to claim 7 , wherein
the intermediate layer includes a conductive layer-side region and a semiconductor layer-side region provided between the conductive layer-side region and the semiconductor layer,
the intermediate layer includes a first region between the first conductive layer and the semiconductor layer, and
a concentration of oxygen in the semiconductor layer-side region of the first region in the first state is lower than a concentration of oxygen in the conductive layer-side region of the first region in the first state.

13. The device according to claim 1 , wherein
a stacked member including the plurality of conductive layers and the plurality of insulating layers extends in a second direction crossing the first direction, and
the semiconductor layer overlaps the plurality of conductive layers in a third direction crossing the first direction and the second direction.

14. The device according to claim 13 , further comprising another semiconductor layer, wherein
at least part of the stacked member is disposed between the semiconductor layer and the another semiconductor layer in the third direction.

15. The device according to claim 1 , further comprising a base member including a first face, wherein
the plurality of conductive layers, the plurality of insulating layers, the semiconductor layer, and the intermediate layer are provided on the first face.

16. The device according to claim 15 , wherein
the base member includes a semiconductor substrate, and
at least a portion of the cont

Assignees

• Toshiba Memory Corp

Inventors

• Fujii Shosuke
• Yamamoto Kazuhiko

Classifications

• G11C16/04

  using variable threshold transistors, e.g. FAMOS · CPC title

• H01L45/085

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L23/5283

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic