Semiconductor device including a stack having a sidewall with recessed and protruding portions

Patent metadata

Field	Value
Publication number	US-9947686-B2
Application number	US-201715456841-A
Country	US
Kind code	B2
Filing date	Mar 13, 2017
Priority date	May 30, 2014
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a stack on the substrate,
the stack extending in a first direction,
the stack including gate electrodes and insulating layers alternately and repeatedly stacked on the substrate,
the stack including a first sidewall and a second sidewall opposite the first sidewall,
the stack including a cutting region extending in the first direction and separating an uppermost gate electrode of the gate electrodes into a first selection gate and a second selection gate,
the first selection gate including first recessed portions and first protruding portions defined by the cutting region; and

channel structures penetrating the stack,
the channel structures in a first row being spaced apart from each other in the first direction,
the channel structures in a second row being spaced apart from each other in the first direction,
the first and second rows of the channel structures being between the first and second sidewalls of the stack such that the cutting region of the stack is between the first and second rows of the channel structures,
each of the first recessed portions being recessed beyond a virtual line connecting outermost points of the channel structures in the first row, when viewed in a plan view, and
each of the outermost points faces each of the first protruding portions, when viewed in the plan view.

2. The semiconductor device of claim 1 , wherein each of the first protruding portions is defined by an adjacent pair of the first recessed portions.

3. The semiconductor device of claim 1 , wherein the cutting region has a zigzag shape, when viewed in the plan view.

4. The semiconductor device of claim 1 , wherein:
the second selection gate includes second recessed portions corresponding to the first protruding portions and second protruding portions corresponding to the first recessed portions
each of the second recessed portions is recessed beyond a virtual line connecting outermost points of the channel structures of the second row, when viewed in the plan view, and
each of the outermost points of the channel structures of the second row faces each of the second protruding portions, when viewed in the plan view.

5. The semiconductor device of claim 1 , wherein:
the second row of channel structures is spaced apart from the first row of channel structures in a second direction crossing the first direction, and
a width of each of the first protruding portions measured in the first direction decreases in the second direction.

6. The semiconductor device of claim 1 , wherein
a third row of the channel structures are adjacent to the first sidewall,
a fourth row of the channel structures are adjacent to the second sidewall, and
the first and second rows of the channel structures are between the third and fourth rows of the channel structures.

7. The semiconductor device of claim 1 , further comprising:
vertical insulators between the stack and the first and second rows of the channel structures,
wherein each of the vertical insulators includes a charge storing layer.

8. The semiconductor device of claim 1 , wherein the gate electrodes fill gap regions between the insulating layers.

9. The semiconductor device of claim 1 , wherein each of the first protruding portions has one of a triangular shape, a trapezoidal shape, and a semi-circular shape.

10. The semiconductor device of claim 1 , wherein:
the first sidewall includes second recessed portions and second protruding portions,
each of the second protruding portions is defined by an adjacent pair of the second recessed portions, and
the second protruding portions are arranged side-by-side with each other in the first direction along the first sidewall.

11. A semiconductor device, comprising:
a stack on a substrate, the stack extending in a first direction, the stack including gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, the stack including a first sidewall and a second sidewall opposite the first sidewall, the stack including a cutting region between the first and second rows, the cutting region extending in the first direction and penetrating an uppermost gate electrode of the gate electrodes;
channel structures penetrating the stack, the channel structures in a first row being spaced apart from each other in the first direction, the channel structures in a second row being spaced apart from each other in the first direction, the first and second rows of the channel structures being between the first and second sidewalls of the stack, wherein
the cutting region is recessed beyond a first virtual line extending in the first direction and connects first outermost points of the channel structures of the first row, when viewed in a plan view,
the cutting region is recessed beyond a second virtual line extending in the first direction and connects second outermost points of the channel structures of the second row, when viewed in the plan view,
each of the first outermost points faces a first region between an adjacent pair of the channel structures of the second row, when viewed in the plan view, and
each of the second outermost points faces a second region between an adjacent pair of the channel structures of the first row, when viewed in the plan view.

12. The semiconductor device of claim 11 , wherein the cutting region has a zigzag shape passing by the first region and the second region, when viewed in the plan view.

13. The semiconductor device of claim 11 , further comprising:
vertical insulators between the stack and the first and second rows of the channel structures,
wherein each of the vertical insulators includes a charge storing layer.

14. The semiconductor device of claim 11 , wherein:
the first row of the channel structures and the second row of the channel structures are spaced apart from each other in a second direction and offset in the first direction such that the channel structures in the first row and the second row are arranged in a zigzag pattern.

15. The semiconductor device of claim 11 , further comprising:
bit lines on the substrate, wherein
the bit lines extend in a second direction crossing the first direction,
the bit lines are spaced apart from each other in the first direction,
some of the bit lines are on top of corresponding channel structures in the first row,
the substrate includes a common source region, and
the gate electrodes are on top of at least a portion of the common source region.

16. A semiconductor device, comprising:
a substrate;
a stack extending in a first direction, the stack including gate electrodes stacked on top of each and spaced apart from each other in a vertical direction on the substrate,
the stack defining a first row of channel holes and a second row of channel holes that extend through the gate electrodes in the vertical direction to the substrate,
the stack including a first sidewall and a second sidewall opposite the first sidewall, the first and second rows of the channel holes being between the first and second sidewalls,
the stack including a cutting region between the first and second rows,
the cutting region extending in the first direction,
the cutting region being at an upper portion of the stack,
the cutting region having a zigzag shape such that the cutting region is recessed beyond a first virtual line extending in the first direction and connecting first outermost points of the channel holes of the first row and recessed beyond a second virtual line extending in the first direction and connecting

Assignees

• Son Byoungkeun
• Shin Yoocheol
• Lee Changhyun
• Kim Hyunjung
• Hyun Chung Il
• Samsung Electronics Co Ltd

Inventors

• Son Byoungkeun
• Shin Yoocheol
• Lee Changhyun
• Kim Hyunjung
• Hyun Chung-Il

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L21/28282

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H10D64/037

  comprising charge-trapping insulators · CPC title