Memory structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12477712-B2
Application number	US-202217747064-A
Country	US
Kind code	B2
Filing date	May 18, 2022
Priority date	May 18, 2022
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A memory structure includes a first pull-up (PU) transistor and a first pull-down (PD) transistor sharing a first gate structure extending in a first direction, and a second PU transistor and a second PD transistor sharing a second gate structure extending in the first direction. The first gate structure has a first PU portion that corresponds with the first PU transistor and a first PD portion that corresponds with the first PD transistor. The second gate structure has a second PU portion that corresponds with the second PU transistor and a second PD portion that corresponds with the second PD transistor. The first and second PU portion each has a first dimension in a second direction perpendicular to the first direction, and the first and second PD portion each has a second dimension in the second direction. The first dimension is greater than the second dimension.

First claim

What is claimed is:

1 . A memory structure comprising:
a first pull-up (PU) transistor and a first pull-down (PD) transistor sharing a first gate structure extending in a first direction; a second PU transistor and a second PD transistor sharing a second gate structure extending in the first direction; and an active area shared by the first PD transistor and the second PD transistor, wherein the first gate structure and the second gate structure are separated in a second direction, wherein the second direction is perpendicular to the first direction; the first gate structure has a first PU portion that corresponds with the first PU transistor and a first PD portion that corresponds with the first PD transistor; the second gate structure has a second PU portion that corresponds with the second PU transistor and a second PD portion that corresponds with the second PD transistor; and the first PU portion and the second PU portion each has a first dimension in the second direction, and the first PD portion and the second PD portion each has a second dimension in the second direction, wherein the first dimension is greater than the second dimension, wherein a distance between the first PD portion and the second PD portion in the second direction is greater than a distance between the first PU portion and the second PU portion in the second direction.

2 . The memory structure of claim 1 , further comprising:
a pass-gate (PG) transistor arranged with the first PD transistor and the second PD transistor in the second direction, wherein the PG transistor has a third gate structure extending in the first direction, wherein a third dimension of the third gate structure in the second direction and the first dimension are the same.

3 . The memory structure of claim 2 , wherein a ratio of the third dimension to the second dimension provides a beta ratio in a range from about 1.1 to about 1.5.

4 . The memory structure of claim 2 , wherein a threshold voltage of the first PD transistor and the second PD transistor is less than a threshold voltage of the PG transistor.

5 . A memory structure comprising:
a first active area and a second active area arranged in a first direction and extending in a second direction, wherein the second direction is perpendicular to the first direction; a first Static Random Access Memory (SRAM) cell comprising: a first gate structure extending in the first direction and having a first pull-down (PD) portion and a first pull-up (PU) portion, wherein the first PD portion and the first PU portion respectively engage the first active area and the second active area to construct a first PD transistor and a first PU transistor; and a second gate structure extending in the first direction and arranged with the first gate structure in the second direction, wherein the second gate structure engages the first active area to construct a first pass-gate (PG) transistor; and a second SRAM cell adjacent to the first SRAM cell in the second direction, the second SRAM cell comprising: a third gate structure extending in the first direction and having a second PD portion and a second PU portion, wherein the second PD portion and the second PU portion respectively engage the first active area and the second active area to construct a second PD transistor and a second PU transistor; a fourth gate structure extending in the first direction and arranged with the third gate structure in the second direction, wherein the fourth gate structure engages the first active area to construct a second pass-gate (PG) transistor; a first source/drain contact between the first PD portion and the second PD portion; and a second source/drain contact between the first PD portion and the second gate structure, wherein a dimension of the first source/drain contact in the second direction is greater than a dimension of the second source/drain contact in the second direction, wherein a gate length of the first PU portion, the second PU portion, the second gate structure, and the fourth gate structure is greater than a gate length of the first PD portion and the second PD portion.

6 . The memory structure of claim 1 , wherein each of the first PU transistor, the second PU transistor, the first PD transistor, and the second PD transistor has nanostructures that are vertically stacked.

7 . The memory structure of claim 1 , wherein a distance between the first PD portion and the second PD portion in the second direction and a distance between the first PU portion and the second PU portion in the second direction are the same.

8 . The memory structure of claim 1 , further comprising:
a first source/drain contact between the first PD portion and the second PD portion; and a second source/drain contact between the first PU portion and the second PU portion, wherein a dimension of the first source/drain contact in the second direction is greater than a dimension of the second source/drain contact in the second direction.

9 . The memory structure of claim 8 , wherein a distance between the first PD portion and the first source/drain contact in the second direction and a distance between the first PU portion and the second source/drain contact in the second direction are the same.

10 . The memory structure of claim 1 , wherein the first PU portion and the second PU portion each has a protrusion portion having a third dimension in the second direction, wherein the first dimension is a sum of the second dimension and the third dimension.

11 . The memory structure of claim 10 , wherein the third dimension is in a range from about 1 nm to about 4 nm.

12 . The memory structure of claim 5 , wherein the dimension of the first source/drain contact is in a range from about 21 nm to about 34 nm and the dimension of the second source/drain contact is in a range from about 20 nm to about 30 nm.

13 . The memory structure of claim 5 , wherein an on-current of the first PD transistor is greater than an on-current of the first PG transistor and an on-current of the second PD transistor that is greater than an on-current of the second PG transistor.

14 . The memory structure of claim 13 , wherein:
a ratio of the on-current of the first PD transistor and the on-current of the first PG transistor and a ratio of the on-current of the second PD transistor and the on-current of the second PG transistor are in a range from about 1.1 to about 1.5.

15 . The memory structure of claim 5 , wherein:
a distance between the first PD portion and the second PD portion in the second direction is greater than a distance between the first PD portion and the second gate structure in the second direction and a distance between the second PD portion and the fourth gate structure in the second direction.

16 . The memory structure of claim 5 , wherein:
a distance between the first PD portion and the second PD portion in the second direction is less than a distance between the first PD portion and the second gate structure in the second direction and a distance between the second PD portion and the fourth gate structure in the second direction.

17 . A memory structure comprising:
a memory cell comprising: a first transistor and a second transistor sharing a first gate structure extending in a first direction; and a third transistor sharing an active area with the second transistor, wherein the active area extends in a second direction perpendicular to the first direction; and a second gate structure extending in the first direction and engaging the active area to construct the third transist

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chou Hung-Ju
• Peng Yuan-Ching

Classifications

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title