Semiconductor device and electronic system including the same

Patent metadata

Field	Value
Publication number	US-12476185-B2
Application number	US-202217868899-A
Country	US
Kind code	B2
Filing date	Jul 20, 2022
Priority date	Nov 30, 2021
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A semiconductor device may include a plurality of gate electrodes apart from each other in a vertical direction on a substrate; a plurality of channel structures penetrating the plurality of gate electrodes and extending in the vertical direction; and a plurality of bit lines arranged on and connected to the plurality of channel structures. The plurality of bit lines may include a plurality of lower bit lines and a plurality of upper bit lines at different vertical levels from each other to constitute at least two layers. The plurality of upper bit lines may be apart from each other in a first horizontal direction and extend in parallel with each other in a second horizontal direction perpendicular to the first horizontal direction. A lower expansion space may be defined between two lower bit lines adjacent to each other among the plurality of lower bit lines.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a plurality of gate electrodes apart from each other in a vertical direction on a substrate; a plurality of channel structures penetrating the plurality of gate electrodes and extending in the vertical direction; and a plurality of bit lines arranged on the plurality of channel structures and connected to the plurality of channel structures,
the plurality of bit lines including a plurality of lower bit lines and a plurality of upper bit lines at different vertical levels from each other to constitute at least two layers,
the plurality of upper bit lines being spaced apart from each other in a first horizontal direction and extending in parallel with each other in a second horizontal direction,
the second horizontal direction being perpendicular to the first horizontal direction,
each of the plurality of lower bit lines including a first lower segment extending in the second horizontal direction, a second lower segment apart from the first lower segment in the first horizontal direction and extending in the second horizontal direction, and a first lower bending portion connecting the first lower segment to the second lower segment,
the first lower bending portion extending at an inclination angle with respect to the second horizontal direction, and
two adjacent lower bit lines, among the plurality of lower bit lines, defining a lower expansion space between the first lower bending portion of a first one of the two adjacent lower bit lines and the first lower bending portion of a second one of the two adjacent lower bit lines.

2 . The semiconductor device of claim 1 , further comprising:
a plurality of bit line contacts between the plurality of channel structures and the plurality of bit lines, wherein the plurality of bit line contacts include a plurality of lower bit line contacts connected to the plurality of lower bit lines and a plurality of upper bit line contacts connected to the plurality of upper bit lines, the first lower bending portion in each of the plurality of lower bit lines provides a plurality of first lower bending portions, the plurality of lower bit lines define a plurality of lower expansion spaces between adjacent first lower bending portions among the plurality of first lower bending portions, each of the plurality of upper bit line contacts connects a corresponding one of the plurality of channel structures to a corresponding one of the plurality of upper bit lines via a corresponding lower expansion space among the plurality of lower expansion spaces.

3 . The semiconductor device of claim 1 , wherein
the first lower segment and the second lower segment in each of the plurality of lower bit lines are arranged at a first pitch in the first horizontal direction, the plurality of upper bit lines are arranged at a second pitch in the first horizontal direction, an expansion width is a width of the lower expansion space in the first horizontal direction, and the expansion width is greater than the first pitch and less than two times the first pitch.

4 . The semiconductor device of claim 3 , wherein
each of the plurality of lower bit lines includes a bending region at an interface between the first lower bending portion and the first lower segment, the bending region in the first one of the two adjacent lower bit lines and the bending region in the second one of the two adjacent lower bit lines are apart from each other in the second horizontal direction by a first distance, and the first distance is greater than the expansion width.

5 . The semiconductor device of claim 4 ,
each of the two adjacent lower bit lines includes a bending part between the first lower segment and the first lower bending portion, the bending part and the first lower bending portion in the first one of the two adjacent lower bit lines are apart by a second distance in the second horizontal direction, and the first lower bending portion in the first one of the two adjacent lower bit lines and the bending part in the second one of the two adjacent lower bit lines are apart from each other by a third distance in the second horizontal direction, and the third distance is greater than the second distance.

6 . The semiconductor device of claim 5 ,
wherein a sum of the second distance and the third distance is equal to the first distance.

7 . The semiconductor device of claim 3 ,
wherein the first pitch and the second pitch have an identical value.

8 . The semiconductor device of claim 7 , wherein
the plurality of upper bit lines include a first upper bit line and a second upper bit line that are adjacent to each other, the first upper bit line and the second upper bit line extend along a first extension line and a second extension line, the first extension line and the second extension line are spaced apart from each other at a distance of the first pitch in the first horizontal direction, the first extension line and the second extension line extend in the second horizontal direction, and in one lower bit line of the plurality of lower bit lines, the first lower segment extends along the first extension line, the second lower segment extends along the second extension line, and the first lower bending portion extends from the first extension line to the second extension line.

9 . The semiconductor device of claim 1 ,
wherein the first lower bending portion of the first one of the two adjacent lower bit lines and the first lower bending portion of the second one of the two adjacent lower bit lines are parallel with each other.

10 . The semiconductor device of claim 9 ,
wherein the first lower bending portion has an inclination angle of about 20 degrees to about 70 degrees with respect to the second horizontal direction.

11 . The semiconductor device of claim 9 , wherein
among the plurality of upper bit lines and the plurality of lower bit lines, some of the plurality of upper bit lines and some of the plurality of lower bit lines constitute one set and are repeated in the first horizontal direction, and in the one set, a number of the plurality of lower bit lines is less than a number of the plurality of upper bit lines.

12 . A semiconductor device comprising:
a gate stack on a substrate and including,
a plurality of gate electrodes spaced apart from each other in a vertical direction on the substrate,
a plurality of channel structures penetrating the plurality of gate electrodes and extending in the vertical direction,
a pair of gate stack separation openings penetrating the plurality of gate electrodes and extending in a first horizontal direction,
a string selection line cut region penetrating at least one gate electrode, the at least one gate electrode including an uppermost gate electrode among the plurality of gate electrodes, and the string selection line cut region extending in the first horizontal direction between the pair of gate stack separation openings, and
a plurality of bit lines respectively arranged on the plurality of channel structures, the plurality of bit lines including a plurality of lower bit lines and a plurality of upper bit lines at different vertical levels from each other to constitute at least two layers,
each of the plurality of lower bit lines including a first lower segment extending in a second horizontal direction, a second lower segment apart from the first lower segment in the first horizontal direction and extending in the second horizontal direction, and a first lower bending portion connecting the first lower segment to the second lower segment and extending at an inclination angle with respect to the seco

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Joonam
• Park Sejun
• Lee Jaeduk
• Kim Gaeun

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title