Three-dimensional semiconductor memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-11024640-B2
Application number	US-201916514557-A
Country	US
Kind code	B2
Filing date	Jul 17, 2019
Priority date	Nov 12, 2018
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. A three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepwise portion on the connection region, an etch stop structure on the stepwise portion of the electrode structure, and a plurality of contact plugs on the connection region, the contact plugs penetrating the etch stop structure and connected to corresponding pad portions of the electrodes, respectively, may be provided. The etch stop structure may include an etch stop pattern and a horizontal dielectric layer, which has have a uniform thickness and covers a top surface and a bottom surface of an etch stop pattern.

First claim

What is claimed is:

1. A three-dimensional semiconductor memory device, comprising:
a substrate including a cell array region and a connection region;
an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepwise portion on the connection region;
an etch stop structure on the stepwise portion of the electrode structure; and
a plurality of contact plugs on the connection region, the contact plugs penetrating the etch stop structure and connected to corresponding pad portions of the electrodes, respectively,
wherein the etch stop structure includes an etch stop pattern and a horizontal dielectric layer, the horizontal dielectric layer having a uniform thickness and covering a top surface and a bottom surface of the etch stop pattern.

2. The device of claim 1 , wherein the horizontal dielectric layer includes:
a first portion covering the top surface of the etch stop pattern; and
a second portion covering the bottom surface of the etch stop pattern,
wherein the first portion and the second portion include a same material.

3. The device of claim 1 , wherein the etch stop pattern includes a dielectric material different from a dielectric material of the horizontal dielectric layer and a dielectric material of the dielectric layers.

4. The device of claim 1 , further comprising:
a vertical structure on the cell array region, the vertical structure penetrating the electrode structure; and
a horizontal blocking dielectric layer covering both a top surface and a bottom surface of the electrodes,
wherein a first portion of the horizontal blocking dielectric layer covers first sidewalls of the electrodes, the first sidewalls of the electrodes being adjacent to the vertical structure.

5. The device of claim 4 , wherein the horizontal dielectric layer includes:
a first portion covering the top surface of the etch stop pattern; and
a second portion covering the bottom surface of the etch stop pattern,
wherein each of the first portion and the second portion of the horizontal dielectric layer has a thickness less than a thickness of the first portion of the horizontal blocking dielectric layer.

6. The device of claim 1 , further comprising:
a buffer dielectric layer between the etch stop pattern and the horizontal dielectric layer.

7. The device of claim 6 , wherein the buffer dielectric layer includes a dielectric material different from a dielectric material of the etch stop pattern and a dielectric material of the horizontal dielectric layer.

8. The device of claim 6 , further comprising:
a common source plug penetrating the electrode structure, the common source plug extending in a first direction and being parallel to the electrode structure,
wherein a portion of the buffer dielectric layer is between the common source plug and second sidewalls of the electrodes, the second sidewalls of the electrodes being adjacent to the common source plug.

9. The device of claim 8 , wherein a thickness of the buffer dielectric layer between the etch stop pattern and the horizontal dielectric layer is greater than a thickness of the buffer dielectric layer on the second sidewalls of the electrodes.

10. The device of claim 1 , further comprising:
a common source plug penetrating the electrode structure, the common source plug extending in a first direction and being parallel to the electrode structure; and
a sidewall spacer between the common source plug and the electrode structure,
wherein the sidewall spacer covers a sidewall of the etch stop pattern.

11. The device of claim 10 , wherein
sidewalls of the electrodes are spaced apart at a first horizontal distance from a sidewall of the common source plug,
the sidewall of the etch stop pattern is spaced apart at a second horizontal distance from the common source plug, and
the second horizontal distance is greater than the first horizontal distance.

12. The device of claim 1 , wherein
each of the electrodes has a first thickness in a second direction perpendicular to a top surface of the substrate, and
the etch stop structure has a second thickness in the second direction on the stepwise portion, the second thickness being greater than the first thickness.

13. The device of claim 1 , further comprising:
a pad dielectric layer between the etch stop structure and the stepwise portion of the electrode structure,
wherein the pad dielectric layer includes a dielectric material different from a dielectric material of the etch stop pattern.

14. A three-dimensional semiconductor memory device, comprising:
a substrate including a cell array region and a connection region;
an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked in a first direction perpendicular to a top surface of the substrate, the electrode structure extending in a second direction parallel to the top surface of the substrate, the electrode structure having a stepwise portion on the connection region;
an etch stop pattern covering the stepwise portion of the electrode structure; and
a common source plug penetrating the electrode structure in the first direction and extending in the second direction,
wherein a first distance between a sidewall of the common source plug and a sidewall of the etch stop pattern is different from a second distance between the sidewall of the common source plug and sidewalls of the electrodes.

15. The device of claim 14 , further comprising:
a plurality of vertical structures penetrating the electrode structure;
a horizontal blocking dielectric layer covering the vertical structures, the sidewalls of the electrodes, and top surfaces and bottom surfaces of the electrodes; and
a horizontal dielectric layer covering both a top surface and a bottom surface of the etch stop pattern,
wherein the horizontal dielectric layer includes a same material as the horizontal blocking dielectric layer,
the electrodes have first sidewalls adjacent to the vertical structures, and
the horizontal dielectric layer includes,
a first portion covering the first sidewalls of the electrodes,
a second portion covering the top surface of the etch stop pattern, and
a third portion covering the bottom surface of the etch stop pattern, each of the second and third portions each having a thickness less than a thickness of the first portion.

16. The device of claim 15 , further comprising:
a buffer dielectric layer between the etch stop pattern and the horizontal dielectric layer,
wherein a portion of the buffer dielectric layer is between the common source plug and the sidewalls of the electrodes, and
wherein a thickness of the buffer dielectric layer between the etch stop pattern and the horizontal dielectric layer is greater than a thickness of the buffer dielectric layer on the sidewalls of the electrodes.

17. The device of claim 14 , wherein the etch stop pattern has a rounded sidewall that is adjacent to the common source plug.

18. The device of claim 14 , further comprising:
a sidewall spacer between the common source plug and the electrode structure,
wherein the sidewall spacer includes a protrusion that horizontally protrudes toward the sidewall of the etch stop pattern.

19. The device of claim 14 , wherein the etch stop pattern includes a dielectric material different from a dielectric material of the dielectric layers.

20. The device of claim 14 , further comprising:
a pad diele

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Sung-Min
• Lim Joon-Sung
• Kim Jiyoung
• Kim Jiwon
• Yang Woosung

Classifications

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H01L27/11521

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic