Vertical-channel ferroelectric flash memory

Patent metadata

Field	Value
Publication number	US-10978485-B2
Application number	US-202016749806-A
Country	US
Kind code	B2
Filing date	Jan 22, 2020
Priority date	Sep 9, 2019
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

A device based on 2T vertical ferroelectric memory cells includes a plurality of select gate lines in a first layer, and a plurality of word lines in a second layer, with a plurality of vertical channel structures disposed operably with the select gate lines and word lines. A vertical channel structure of a memory cell in the plurality is disposed orthogonally relative to a corresponding select gate line and a corresponding word line, and forms a channel for the vertical select transistor and the vertical ferroelectric memory transistor. Ferroelectric material is disposed at cross-points between the vertical channel structure and the corresponding word line. A gate dielectric material is disposed at cross-points between the vertical channel structure and the corresponding select gate line. A NOR architecture memory uses the 2T vertical ferroelectric memory cells.

First claim

What is claimed is:

1. A memory comprising:
a plurality of memory cells, each memory cell in the plurality of memory cells including a vertical select transistor having a vertical channel disposed orthogonally relative to a corresponding select gate line and a vertical ferroelectric memory transistor having a vertical channel disposed orthogonally relative to a corresponding word line, the vertical select transistor and vertical ferroelectric memory transistor in series between a bit line and a reference line.

2. The memory of claim 1 , including:
a plurality of select gate lines and a plurality of word lines;
a plurality of vertical channel structures, each vertical channel structure in the plurality disposed orthogonally relative to a corresponding select gate line in the plurality of select gate lines to form said vertical channel for the vertical select transistor, and disposed orthogonally relative to a corresponding word line in the plurality of word lines to form said vertical channel for the vertical ferroelectric memory transistor.

3. The memory of claim 1 , including
a plurality of select gate lines and a plurality of word lines;
a plurality of vertical channel structures, each vertical channel structure in the plurality disposed orthogonally relative to and surrounded by a corresponding select gate line in the plurality of select gate lines to form said vertical channel for the vertical select transistor and disposed orthogonally relative to and surrounded by a corresponding word line in the plurality of word lines to form said vertical channel for the vertical ferroelectric memory transistor.

4. The memory of claim 1 , wherein the vertical ferroelectric memory transistor comprises said vertical channel, a layer of ferroelectric material, and a layer of word line material.

5. The memory of claim 4 , wherein the layer of ferroelectric material comprises hafnium oxide.

6. The memory of claim 1 , wherein the plurality of memory cells is configured in a NOR architecture.

7. The memory of claim 1 , wherein the plurality of memory cells is disposed on a substrate, the substrate comprising logic circuitry, and the plurality of memory cells is arranged in an array overlying the logic circuitry.

8. The memory of claim 1 , wherein the plurality of memory cells is disposed in an array on a substrate, and including logic circuitry overlying the array.

9. The memory of claim 1 , including biasing circuitry to apply read, program and erase operations to the plurality of memory cells.

10. An integrated circuit memory, comprising:
a substrate;
a reference conductor on the substrate;
a stack including a select gate conductor layer and a word line conductor layer over the reference conductor on the substrate;
a plurality of vertical channel pillars arranged orthogonally relative to the select gate conductor layer and the word line conductor layer in the stack, and contacting the reference conductor;
ferroelectric memory material at cross-points of the vertical channel pillars and the word line conductor layer;
select gate dielectric material at cross-points of the vertical channel pillars and the select gate conductor layer; and
a plurality of bit lines over the plurality of vertical channel pillars and in contact with vertical channel pillars.

11. The integrated circuit memory of claim 10 , wherein the reference conductor on the substrate comprises a doped semiconductor material.

12. The integrated circuit memory of claim 10 , wherein the plurality of vertical channel pillars are surrounded by select gate conductor material in the select gate conductor layer and by word line conductor material in the word line conductor layer.

13. The integrated circuit memory of claim 10 , wherein the select gate conductor layer is beneath the word line conductor layer in the stack.

14. The integrated circuit memory of claim 10 , including control and biasing circuits to program data by applying an electric field to set a residual polarity in the ferroelectric memory material.

15. The integrated circuit memory of claim 10 , including a dielectric layer between the ferroelectric memory material and the vertical channel pillars, and a conductive buffer layer between the ferroelectric memory material and the word line conductor layer.

16. The integrated circuit memory of claim 10 , wherein the ferroelectric material comprises hafnium oxide.

17. The integrated circuit memory of claim 10 , wherein memory comprising the plurality of vertical channel pillars is configured in a nor architecture.

18. The integrated circuit memory of claim 10 , including logic circuitry, and wherein the stack overlies the logic circuitry.

19. The integrated circuit memory of claim 10 , including logic circuitry, and wherein the logic circuitry overlies the stack.

20. A method for manufacturing a memory comprising:
forming a plurality of select gate lines and a plurality of word lines;
forming a plurality of vertical channel structures, each vertical channel structure in the plurality disposed orthogonally relative to a corresponding select gate line in the plurality of select gate lines to form a channel for the vertical select transistor, and disposed orthogonally relative to a corresponding word line in the plurality of word lines to form a channel for the vertical ferroelectric memory transistor;
forming ferroelectric memory material at cross-points of the vertical channel pillars and the word line conductor layer; and
forming select gate dielectric material at cross-points of the vertical channel pillars and the select gate conductor layer.

Assignees

• Macronix Int Co Ltd

Inventors

• Lue Hang-Ting

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/689

  having ferroelectric layers · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title