Vertical memory devices

Patent metadata

Field	Value
Publication number	US-10242997-B2
Application number	US-201615223255-A
Country	US
Kind code	B2
Filing date	Jul 29, 2016
Priority date	Oct 29, 2015
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

First claim

What is claimed is:

1. A vertical memory device, comprising:
a substrate;
a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate;
a plurality of gate lines surrounding a predetermined number of channels from among the channels, wherein the gate lines are arranged and spaced apart from one another along the first direction and a direction parallel to the top surface of the substrate;
a plurality of common wirings electrically connected to the gate lines, wherein each common wiring is electrically connected to corresponding gate lines at a same level from among the gate lines; and
a plurality of signal wirings, wherein each signal wiring is electrically connected to at least one of the gate lines via one of the common wirings,
wherein the signal wirings comprise first signal wirings and second signal wirings the common wirings comprise a first group and a second group, and the gate lines comprise an upper group and a lower group,
wherein the first group of common wiring electrically connects the second signal wirings, which are disposed above the first signal wirings, to the upper group of gate lines, and the second group of common wirings electrically connects the first signal wirings, which are disposed below the second signal wirings, to the lower group of gate lines,
wherein the gate lines are stacked along the first direction, the gate lines extend in a second direction substantially parallel to the top surface of the substrate, and the common wirings extend in a third direction substantially parallel to the top surface of the substrate and crossing the second direction.

2. The vertical memory device of claim 1 , wherein the signal wirings extend in a different direction than the common wirings.

3. The vertical memory device of claim 2 , wherein the signal wirings extend in the second direction.

4. A vertical memory device, comprising:
a substrate;
a plurality of gate line stack structures disposed on the substrate, wherein each gate line stack structure comprises:
a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate; and
a plurality of gate lines surrounding outer sidewalls of the channels, wherein the gate lines are stacked and spaced apart from one another along the first direction;

a plurality of common wirings extending over different gate line stack structures from among the gate line stack structures, wherein each common wiring is electrically connected to corresponding gate lines at a same level from among the gate lines; and
a plurality of signal wirings, wherein each signal wiring is electrically connected to at least one of the gate lines via one of the common wirings,
wherein the signal wirings comprise first signal wirings and second signal wiring, the common wirings comprise a first group and a second group, and the gate lines comprise an upper group and a lower group,
wherein the first group of common wirings electrically connects the second signal wirings, which are disposed above the first signal wirings, to the upper group of gate lines, and the second group of common wirings electrically connects the first signal wirings, which are disposed below the second signal wirings, to the lower group of gate line,
wherein the plurality of common wirings is disposed below the plurality of signal wirings.

5. The vertical memory device of claim 4 ,
wherein each gate line stack structure has a stepped shape, and each gate line stack structure comprises step portions defined by the gate lines at different levels,
wherein the substrate comprises a cell region, a peripheral circuit region, and an extension region disposed between the cell region and the peripheral circuit region,
wherein the signal wirings extend from the extension region to the peripheral circuit region.

6. The vertical memory device of claim 5 , wherein the signal wirings are disposed over the common wirings, and the signal wirings extend in a different direction than the common wirings.

7. The vertical memory device of claim 5 , further comprising:
a plurality of first contacts disposed on the step portions,
wherein first contacts from among the first contacts that are electrically connected to step portions at a same level of the step portions are connected to one another by a same one of the common wirings.

8. The vertical memory device of claim 7 , wherein the first contacts are arranged in a zigzag configuration along a direction of the signal wirings.

9. The vertical memory device of claim 7 , further comprising:
a plurality of second contacts connecting the signal wirings and the common wirings, wherein one of the second contacts is provided per each of the common wirings.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Chang-Min
• Lim Ju-Young
• Ahn Su-Jin

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H01L27/11556

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L23/5283

  Electricity · mapped topic