Staggered semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10868029-B2
Application number	US-201816127962-A
Country	US
Kind code	B2
Filing date	Sep 11, 2018
Priority date	Mar 22, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a substrate;
a stacked body provided above the substrate, the stacked body including a plurality of electrode layers stacked to be separated from each other;
a plurality of columnar portions extending through the stacked body in a stacking direction of the plurality of electrode layers of the stacked body, each of the plurality of columnar portions including a semiconductor portion;
a plurality of interconnects extending in a first direction and being electrically connected to the semiconductor portions of the plurality of columnar portions, the first direction being parallel to an upper surface of the substrate; and
a plurality of connection portions provided between the plurality of columnar portions and the plurality of interconnects, the plurality of connection portions including a connection portion connected correspondingly to one columnar portion of the plurality of columnar portions and one interconnect of the plurality of interconnects,
wherein a portion of a first connection portion extending in the first direction overlaps a portion of a second connection portion extending in the first direction when viewed from a second direction perpendicular to the stacking direction and the first direction,
the first connection portion is connected to a first interconnect of the plurality of interconnects,
the second connection portion is connected to a second interconnect of the plurality of interconnects, and
the first interconnect and the second interconnect are the nearest interconnects to each other in the second direction.

2. The device according to claim 1 , wherein configurations of the first connection portion and the second connection portion are ellipses when viewed from the stacking direction.

3. The device according to claim 1 , wherein
lower surfaces of the plurality of connection portions contact the semiconductor portions of the plurality of columnar portions, and
upper surfaces of the plurality of connection portions contact the plurality of interconnects.

4. The device according to claim 1 , wherein lengths in the first direction of the plurality of connection portions decrease toward the plurality of columnar portions.

5. The device according to claim 1 , wherein the plurality of connection portions includes first portions contacting the semiconductor portions of the plurality of columnar portions, and second portions provided above the first portions and contacting the plurality of interconnects.

6. The device according to claim 1 , wherein
the plurality of columnar portions are provided in a plurality of columns arranged along the first direction, and
the columnar portions of each column are arranged along the second direction.

7. The device according to claim 1 , wherein
the semiconductor portions of the plurality of columnar portions extend in the stacking direction, and
one of the plurality of columnar portions includes a charge storage film provided between one of the semiconductor portions and one of the plurality of electrode layers.

Assignees

• Toshiba Memory Corp

Inventors

• Iijima Jun
• Tagami Masayoshi
• Usui Takamasa
• Nishimura Takahito

Classifications

• G11C11/24

  using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40) · CPC title

• H01L27/11578 Primary

  Electricity · mapped topic

• H01L27/11568

  Electricity · mapped topic

• H10B43/20 Primary

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title