Semiconductor device active region profile and method of forming the same

Patent metadata

Field	Value
Publication number	US-12471306-B2
Application number	US-202418745323-A
Country	US
Kind code	B2
Filing date	Jun 17, 2024
Priority date	May 12, 2021
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

First claim

What is claimed is:

1 . A method comprising:
providing a semiconductor stack over a substrate, the semiconductor stack having first and second semiconductor layers stacked in an interleaving fashion, the first and second semiconductor layers having different materials; etching the semiconductor stack as part of a first etching process; etching the semiconductor stack as part of a second etching process, wherein the second etching process has a lateral etch rate greater than that of the first etching process; and repeating the first etching process and the second etching process to form a trench that extends into the substrate; and forming a cladding layer in the trench, wherein a sidewall of the cladding layer and a horizontal portion of the cladding layer form an angle less than 90 degrees.

2 . The method of claim 1 , wherein each of the second etching process is longer than the first etching process by about 1.3 to about 1.6 times.

3 . The method of claim 1 , wherein each of the first etching process uses a chlorine-containing gas and each of the second etching process uses a fluoride-containing gas.

4 . The method of claim 1 , wherein the first semiconductor layers are formed of a same material as the cladding layer, and the second semiconductor layers are formed of a same material as the substrate.

5 . The method of claim 1 , wherein before the forming of the cladding layer, further comprising:
forming a shallow trench isolation (STI) structure in the trench, the STI structure having a top surface parallel with a top surface of the substrate, and the top surface of the STI structure is below the top surface of the substrate, wherein the horizontal portion of the cladding layer is formed on the top surface of the STI structure.

6 . The method of claim 5 , further comprising:
etching the horizontal portion of the cladding layer to expose the top surface of the STI structure; and forming a dielectric fin in the trench and on the exposed top surface of the STI structure.

7 . The method of claim 1 , further comprising:
forming a dielectric fin in the trench and laterally between sidewalls of the cladding layer; forming a gate trench by selectively etching the first semiconductor layers and the cladding layer with minimal etching to the second semiconductor layers; and forming a metal gate stack in the gate trench that wraps around each of the second semiconductor layers.

8 . The method of claim 7 , wherein the forming of the dielectric fin includes:
depositing a dielectric liner in the trench and over the cladding layer; depositing a dielectric fill layer over the dielectric liner; recessing the dielectric fill layer; and forming a dielectric cap over the recessed dielectric fill layer.

9 . The method of claim 8 , wherein the dielectric liner is formed of a nitride-based dielectric, the dielectric fill layer is formed of an oxide-based dielectric, and the dielectric cap is formed of a high-k dielectric material.

10 . The method of claim 1 , further comprising:
flushing a byproduct from the semiconductor stack after etching the semiconductor layer stack as part of the second etching process; and repeating the flushing after each repetition of the second etching process.

11 . A semiconductor structure, comprising:
a substrate; a plurality of channels of a semiconductor material vertically stacked over the substrate; a gate stack disposed on the plurality of channels and extended to wrap around each of the plurality of channels, wherein the gate stack includes a gate dielectric layer and a gate electrode; and a dielectric fin disposed adjacent the plurality of channels of the semiconductor material, wherein the dielectric fin have slanted sidewalls such that a top portion of the dielectric fin is more narrow than a bottom portion of the dielectric fin.

12 . The semiconductor structure of claim 11 , wherein the plurality of channels forms a stack of channels that increases in width from a bottommost channel to a topmost channel of the plurality of channels.

13 . The semiconductor structure of claim 12 , wherein the bottommost channel of the plurality of channels spans about 18 nm to 22 nm, and the topmost channel of the plurality of channels spans about 24 nm.

14 . The semiconductor structure of claim 11 , wherein the top portion of the dielectric fin includes a different dielectric material from the bottom portion of the dielectric fin.

15 . The semiconductor structure of claim 14 , wherein the top portion of the dielectric fin includes a high-k dielectric.

16 . The semiconductor structure of claim 11 , wherein the dielectric fin includes a dielectric liner surrounding one or more dielectric fill layers, and the dielectric liner interfaces sidewalls of the gate stack.

17 . A semiconductor structure, comprising:
a substrate; active regions protruding from the substrate, each active region includes a stack of semiconductor channels; isolation structures between lower portions of the active regions; and dielectric fins landing on the isolation structures and disposed between upper portions of the active regions, wherein each of the active regions have a top width and a bottom width, and the top width of each of the active regions is greater than the bottom width of each of the active regions, wherein each of the dielectric fins have a top width and a bottom width, and the top width of each of the dielectric fins is smaller than the bottom width of each of the dielectric fins.

18 . The semiconductor structure of claim 17 , further comprising:
a gate stack disposed over the active regions and wrapping around each semiconductor channel of the stack of semiconductor channels.

19 . The semiconductor structure of claim 18 , wherein the gate stack further lands on the dielectric fins.

20 . The semiconductor structure of claim 18 , wherein top surfaces of the dielectric fins are above top surfaces of each stack of semiconductor channels of the active regions.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chu Feng-Ching
• Lee Wei-Yang
• Lin Chia-Pin

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P50/242 Primary

  of Group IV materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/0194

  the stacked channels having different properties · CPC title