Moisture seal coating of hybrid bonded stacked die package assembly

Patent metadata

Field	Value
Publication number	US-12469801-B2
Application number	US-202117554471-A
Country	US
Kind code	B2
Filing date	Dec 17, 2021
Priority date	Dec 17, 2021
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

Stacked die assemblies having a moisture sealant layer according to embodiments are described herein. A microelectronic package structure having a first die with a second and an adjacent third die on the first die. Each of the second and third die comprise hybrid bonding interfaces with the first die. A first layer is on a region of the first die adjacent sidewalls of the second and the third dies, and adjacent an edge portion of the first die. The first layer comprises a diffusion barrier material A second layer is over the first layer, the second layer, wherein a top surface of the second layer is substantially coplanar with the top surfaces of the second and third dies. The first layer provides a hermetic moisture sealant layer for stacked die package structures.

First claim

What is claimed is:

1 . A microelectronic package structure comprising:
a first die comprising one or more first conductive structures and a first die dielectric material between individual ones of the first conductive structures: a second die comprising one or more second conductive structures directly on a first set of the one or more first conductive structures; a third die adjacent to the second die, the third die comprising one or more third conductive structures directly on a second set of the one or more first conductive structures; a first layer, wherein a first portion of the first layer is on a sidewall of the third die, and wherein a second portion of the first layer, adjacent the first portion of the first layer, is directly on the second set of the one or more first conductive structures, wherein about a 90 degree angle is between the first portion and the second portion, and wherein a third portion of the first layer adjacent to the second portion comprises a step structure, wherein a portion of the step structure is directly on an active region of the first die, wherein the active region comprises circuitry structures, and wherein the step structure comprises a first portion on a sidewall of the first die dielectric material and a second portion directly on the active region, wherein about a 90 degree angle is between the first portion and the second portion; and a second layer over the first layer, wherein the second layer comprises a surface that is substantially coplanar with top surfaces of the second die and the third die.

2 . The microelectronic package structure of claim 1 , wherein the first layer comprises at least one of silicon carbide, silicon carbon nitride, copper, aluminum, or carbon.

3 . The microelectronic package structure of claim 1 , wherein the first layer comprises a diffusion barrier layer.

4 . The microelectronic package structure of claim 1 wherein the first layer comprises one or more of alumina, silicon, oxygen, or nitrogen.

5 . The microelectronic package structure of claim 1 wherein the second layer comprises a mold material.

6 . The microelectronic package structure of claim 1 wherein the microelectronic package structure comprises a portion of a hybrid bond 3D stacked die package.

7 . The microelectronic package structure of claim 1 wherein the first layer comprises a thickness between 50 nm to 100 nm.

8 . The microelectronic package structure of claim 1 wherein a third layer is on a surface of the second die and on a surface of the third die, wherein the third layer comprises gold, wherein the third layer is over the first layer.

9 . A computer system comprising;
a power supply; one or more integrated circuit packages coupled to the power supply, wherein at least one of the integrated circuit packages further comprises: a first die comprising one or more first conductive structures and a first die dielectric material between individual ones of the first conductive structures: a second die comprising one or more second conductive structures directly on a first set of the one or more first conductive structures; a third die adjacent to the second die, the third die comprising one or more third conductive structures directly on a second set of the one or more first conductive structures; and a layer directly on the first die adjacent a sidewall of the second die, wherein the layer comprises a thickness of between 50 nm to 100 nm, and wherein a portion of the layer adjacent to the third die comprises a step structure, wherein a bottom portion of the step structure is directly on an active region of the first die, wherein the step structure comprises a first portion on a sidewall of the first die dielectric material and a second portion directly on the active region, wherein about a 90 degree angle is between the first portion and the second portion.

10 . The computer system of claim 9 , further comprising a fill layer directly on the layer, wherein the fill layer comprises a surface that is substantially coplanar with top surfaces of the first die and the second die.

11 . The computer system of claim 9 wherein the layer comprises a multilayer diffusion barrier, wherein a first diffusion layer comprises a thickness of 50 to 100 nm, and a second diffusion layer comprises a thickness of 50 to 150 nm.

12 . The computer system of claim 11 wherein the first diffusion layer comprises silicon and nitrogen, and the second diffusion layer comprises an alumina material.

13 . The computer system of claim 9 wherein a first portion of the step structure is on a first die dielectric material sidewall, wherein the first portion and the bottom portion are above the active region.

14 . A method of fabricating an integrated circuit (IC) package structure, the method comprising:
receiving a first die with a second die attached to a first region of the first die and a third die attached to a second region of the first die, wherein the first die comprises one or more first conductive structures and a first die dielectric material between individual ones of the first conductive structures; forming a layer on sidewalls of the second die, on sidewalls of the third die and on the one or more first conductive structures at a surface of the first die between the second die and the third die, and directly on an active region of the first die adjacent to the third die, wherein the layer comprises a diffusion barrier, wherein a portion of the layer comprises a step structure, the step structure comprising a first portion on a sidewall of the first die dielectric material and a second portion directly on the active region, wherein about a 90 degree angle is between the first portion and the second portion; and forming a fill material on the layer, wherein the fill material comprises a surface that is substantially coplanar with top surfaces of the second die and the third die.

15 . The method of claim 14 wherein forming the layer comprises forming a diffusion barrier material directly on a corner region between the first die dielectric material and a sidewall of the third die.

16 . The method of claim 14 wherein forming the layer comprises forming a material comprising at least one of silicon, nitrogen or alumina, wherein the layer comprises a thickness of less than 150 nm.

17 . The method of claim 14 wherein forming the layer comprises forming a diffusion barrier material on a sidewall of the first die dielectric material and directly on the active region of the first die.

18 . The method of claim 17 wherein an approximately 90 degree angle is between the sidewall of the first die dielectric material and the active region.

Assignees

• Intel Corp

Inventors

• Mallik Debendra
• Kabir Mohammad Enamul
• Deshpande Nitin
• Karhade Omkar
• Sarkar Arnab
• Agraharam Sairam
• Pelto Christopher
• Kim Gwang-Soo
• Mahajan Ravindranath

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10P90/1914

  using bonding · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title