Thermally conductive structure for heat dissipation in semiconductor packages

Patent metadata

Field	Value
Publication number	US-9576930-B2
Application number	US-201314075139-A
Country	US
Kind code	B2
Filing date	Nov 8, 2013
Priority date	Nov 8, 2013
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a wafer carrier having an adhesive layer on an upper surface of the wafer carrier;
at least one chip attached to the wafer carrier through the adhesive layer;
an insulating barrier layer formed over the at least one chip and exposed regions of the adhesive layer;
a thermally conductive layer formed over the insulating barrier layer, the thermally conductive layer at least partially encapsulating the at least one chip, wherein the thermally conductive layer comprises a thermally conductive path which dissipates heat to the ambient environment; and
a molding compound formed over the thermally conductive layer, wherein the molding compound has a composition that differs from a composition of the thermally conductive layer, wherein the molding compound directly contacts the insulating barrier layer over the at least one chip.

2. The semiconductor package of claim 1 , further comprising:
a thermal interface material (TIM) covering an upper surface of the thermally conductive layer; and
a heat sink mounted on the TIM, wherein the heat sink is thermally coupled to the thermally conductive layer through the TIM.

3. The semiconductor package of claim 1 , wherein the insulating barrier layer comprising at least one of the following:
an oxide, a high-k dielectric material, SiN x , SiON x , SiO x , TaN, TiN, carbides, a SOG, BCB, PBO, a polyimide or another polymer; wherein the insulating barrier layer has a thickness ranging from about 10 Angstroms to about 10,000 Angstroms.

4. The semiconductor package of claim 1 , wherein the thermally conductive layer comprises a plurality of thermally conductive filler material, wherein the thermally conductive filler material comprises a filler material from at least one or more of metallic material, semiconductor material, solder material, carbon nano tubes, carbon nano fibers, or graphite and wherein the thermally conductive filler material comprises from about 70% of the thermally conductive layer to about 95% of the thermally conductive layer.

5. The semiconductor package of claim 1 , further comprising:
a thermal interface material (TIM) covering an upper surface of the molding compound; and
a heat sink mounted on the TIM.

6. The semiconductor package of claim 4 , wherein the metallic material comprises at least one of aluminum (Al), copper (Cu), silver (Ag), gold (Au), AlN or Al 2 O 3 .

7. The semiconductor package of claim 4 , wherein the solder material comprises at least one member selected from tin, lead, copper, antimony or silver.

8. The semiconductor package of claim 1 , wherein the thermally conductive layer comprises a substantially solid layer, wherein the substantially solid layer comprises one or more of copper or a copper alloy.

9. The semiconductor package of claim 1 , wherein the thermally conductive layer comprises a thermally conductive adhesive layer, wherein the thermally conductive adhesive layer comprising silver (Ag), copper (Cu), gold (au), aluminum (Al), carbon nanotubes, or graphite.

10. The semiconductor package of claim 1 , wherein the thermally conductive layer comprises a polymer having a conductive filler material.

11. The semiconductor package of claim 10 , wherein the conductive filler material comprises one or more of carbon nanotubes, graphite, graphene, or metal particles.

12. A semiconductor package, comprising:
an adhesive layer overlaying a wafer carrier;
at least one chip physically coupled to the wafer carrier through the adhesive layer, the at least one chip leaving an upper surface of the adhesive layer exposed, the exposed upper surface of the adhesive layer being planar and being in parallel with an upper surface of the wafer carrier;
an insulating barrier layer formed over the at least one chip and over the exposed upper surface of the adhesive layer, wherein the insulating barrier layer encapsulates the at least one chip coupled to the wafer carrier;
a thermally conductive layer over the insulating barrier layer, wherein the thermally conductive layer defines a thermally conductive path configured to transfer heat to the surrounding environment; and
a molding compound formed over the thermally conductive layer, wherein the molding compound has a composition that differs from a composition of the thermally conductive layer.

13. The semiconductor package of claim 12 , further comprising:
a thermal interface material (TIM) covering a top surface of the thermally conductive layer.

14. The semiconductor package of claim 13 , further comprising:
a heat sink mounted on the TIM, wherein the heat sink is thermally coupled to the thermally conductive layer through the TIM.

15. The semiconductor package of claim 12 , wherein the insulating barrier layer comprising at least one of the following:
an oxide, a high-k dielectric material, SiN x , SiON x , SiO x , TaN, TiN, carbides, a SOG, BCB, PBO, a polyimide or another polymer; wherein the insulating barrier layer has a thickness ranging from about 10 Angstroms to about 10,000 Angstroms.

16. The semiconductor package of claim 12 , wherein the thermally conductive layer comprises a plurality of thermally conductive filler materials, the thermally conductive filler materials comprise a filler material from at least one or more of metallic material, semiconductor material, solder material, carbon nano tubes, carbon nano fibers, or graphite.

17. The semiconductor package of claim 12 , wherein the thermally conductive layer comprises a thermally conductive adhesive layer comprising silver (Ag), copper (Cu), gold (au), aluminum (Al), carbon nanotubes, or graphite.

18. The semiconductor package of claim 1 , wherein at least two chips, which exhibit a difference in height between their uppermost surfaces, are adhered to the wafer carrier through the adhesive layer, and wherein the thermally conductive layer has a height which spans the difference in height between the uppermost surfaces of the at least two chips.

19. The semiconductor package of claim 12 , wherein the molding compound directly contacts the insulating barrier layer over the at least one chip.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tseng Chun-Hao
• Kuo Ying-Hao
• Yee Kuo-Chung

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/354

  comprising polymers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W90/00

  Package configurations · CPC title