High bandwidth optical interconnection architectures
US-12517314-B2 · Jan 6, 2026 · US
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Sarkar Arnab patents
Sarkar Arnab is listed as an inventor on 28 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Sarkar Arnab |
| Total patents | 28 |
| First publication | Feb 2, 2016 |
| Latest publication | Jan 6, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Moisture seal coating of hybrid bonded stacked die package assembly
US-12469801-B2 · Nov 11, 2025 · US
Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
US-2025029908-A1 · Jan 23, 2025 · US
Slit fiducials for integrated circuit device alignment
US-2025006651-A1 · Jan 2, 2025 · US
Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
US-12142553-B2 · Nov 12, 2024 · US
Fiducial marks for verifying alignment accuracy of bonded integrated circuit dies
US-2024006332-A1 · Jan 4, 2024 · US
Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
US-2023260884-A1 · Aug 17, 2023 · US
Electroless metal-defined thin pad first level interconnects for lithographically defined vias
US-11728258-B2 · Aug 15, 2023 · US
Moisture seal coating of hybrid bonded stacked die package assembly
US-2023197637-A1 · Jun 22, 2023 · US
Dummy die placement within a dicing street of a wafer
US-2023197520-A1 · Jun 22, 2023 · US
Recent patents
Latest publications not already listed above.
Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
US-11676889-B2 · Jun 13, 2023 · US
High bandwidth optical interconnection architectures
US-2022155539-A1 · May 19, 2022 · US
Integrated circuit package with through void guard trace
US-2022148981-A1 · May 12, 2022 · US
Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
US-2022130743-A1 · Apr 28, 2022 · US
Electroless metal-defined thin pad first level interconnects for lithographically defined vias
US-2022084927-A1 · Mar 17, 2022 · US
Integrated circuit package with through void guard trace
US-11264338-B2 · Mar 1, 2022 · US
Electroless metal-defined thin pad first level interconnects for lithographically defined vias
US-11257745-B2 · Feb 22, 2022 · US
Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
US-11257743-B2 · Feb 22, 2022 · US
Electroless metal-defined thin pad first level interconnects for lithographically defined vias
US-2020258827-A1 · Aug 13, 2020 · US
Hybrid technology 3-d die stacking
US-2020066640-A1 · Feb 27, 2020 · US
Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
US-2019371719-A1 · Dec 5, 2019 · US
Via architecture for increased density interface
US-10475736-B2 · Nov 12, 2019 · US
Integrated circuit package with through void guard trace
US-2019295961-A1 · Sep 26, 2019 · US
Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
US-10418312-B2 · Sep 17, 2019 · US
Via architecture for increased density interface
US-2019096798-A1 · Mar 28, 2019 · US
Package substrate first-level-interconnect architecture
US-10121679-B1 · Nov 6, 2018 · US
Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
US-2018226331-A1 · Aug 9, 2018 · US
Method of manufacturing protein beverages and denaturizing loop apparatus and system
US-9247767-B2 · Feb 2, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 27 |
| Tetra Laval Holdings & Finance | 2 |
| Pepsico Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W70/635 | 18 |
| H10W90/724 | 18 |
| H01L23/49827 | 15 |
| H10W42/00 | 14 |
| H10W90/00 | 12 |