Method of packaging stacked dies on wafer using flip-chip bonding

Patent metadata

Field	Value
Publication number	US-9704841-B2
Application number	US-201414226802-A
Country	US
Kind code	B2
Filing date	Mar 26, 2014
Priority date	Mar 26, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A wafer package process includes the following steps. A wafer with a plurality of first dies is provided. A plurality of second dies are bonded on the first dies by using flip chip technology, wherein the size of the first die is larger than that of the second die. A molding material is formed to entirely cover the second dies and the wafer. A through via is formed in the molding material. A conductive material is formed to fill the through via onto the molding material.

First claim

What is claimed is:

1. A wafer package process, comprising:
providing a wafer with a plurality of first dies comprising at least a bond pad and an inter-dielectric layer, wherein a MOS transistor is in the inter-dielectric layer;
bonding a plurality of second dies on the first dies by using flip chip technology, wherein the size of the first die is larger than that of the second die;
forming a molding material to entirely cover the second dies and the wafer;
forming a through via only in the molding material and exposing the bond pad, wherein a top surface of the bond pad trims a top surface of the inter-dielectric layer;
forming a conductive material filling the through via as well as onto the molding material, wherein the step of forming the conductive material comprises: sequentially forming a barrier layer, a seed layer and a main conductive material on the molding material; performing a planarization process to planarize the main conductive material, the seed layer and the barrier layer until the molding material is exposed; and forming additional conductive material on the molding material; and
performing a sawing process to separate the wafer into many parts after the conductive material is formed.

2. The wafer package process according to claim 1 , wherein the molding material comprises polymer or benzocyclobutene (BCB).

3. The wafer package process according to claim 1 , wherein the molding material is formed by coating, injection molding or extrusion.

4. The wafer package process according to claim 1 , wherein the step of forming the through via in the molding material comprises:
forming the through via in the molding material using a photolithography process and an etching process.

5. The wafer package process according to claim 4 , further comprising:
performing a curing process on the molding material after the through via is formed.

6. The wafer package process according to claim 1 , wherein the conductive material on the molding material comprises a redistribution layer.

7. The wafer package process according to claim 1 , further comprising:
forming a passivation layer entirely covering the first die and the second die after the conductive material is formed.

8. The wafer package process according to claim 1 , further comprising:
forming at least a bump on the conductive material after the conductive material is formed.

9. The wafer package process according to claim 1 , further comprising:
bonding these parts on carriers, respectively, by using flip chip technology.

10. The wafer package process according to claim 1 , further comprising:
bonding a plurality of third dies on the plurality of first dies by using flip chip technology.

11. The wafer package process according to claim 10 , wherein the second dies and the third dies are different functional dies.

12. The wafer package process according to claim 10 , wherein the second dies and the third dies are bonded on the first dies through an assembly process.

13. The wafer package process according to claim 12 , wherein the assembly process comprises a Cu to Cu bonding process, a micro-bonding process or an oxide fusion bonding process.

14. The wafer package process according to claim 10 , wherein the second dies and the third dies are arranged regularly and alternately, and each second die and each third die is correspondingly bonded to each first die.

15. The wafer package process according to claim 14 , further comprising:
performing a sawing process to separate the wafer into many parts after the conductive material is formed, wherein each part has one of the first dies paired with one of the second dies and one of the third dies.

Assignees

• United Microelectronics Corp

Inventors

• Kuo Chien-Li

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title