Semiconductor devices having vertical channel transistor structures and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-12464770-B2
Application number	US-202217578893-A
Country	US
Kind code	B2
Filing date	Jan 19, 2022
Priority date	May 25, 2021
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A semiconductor device includes: a conductive line that extends in a first direction on a substrate; an insulating pattern layer on the substrate and having a trench that extends in a second direction, the trench having an extension portion that extends into the conductive line; a channel layer on opposite sidewalls of the trench and connected to a region, exposed by the trench, of the conductive line; first and second gate electrodes on the channel layer, and respectively along the opposite sidewalls of the trench; a gate insulating layer between the channel layer and the first and second gate electrodes; a buried insulating layer between the first and second gate electrodes within the trench; and a first contact and a second contact, respectively buried in the insulating pattern layer, and respectively connected to upper regions of the channel layer.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate; a conductive line that extends in a first direction on the substrate; an insulating pattern layer on the substrate that covers the conductive line, the insulating pattern layer having a trench that extends in a second direction that crosses the first direction, the trench having an extension portion that extends into the conductive line; a channel layer on opposite sidewalls of the trench and connected to a region of the conductive line that is exposed by the extension portion of the trench; a first gate electrode and a second gate electrode on the channel layer, and respectively arranged along the opposite sidewalls of the trench; a gate insulating layer between the channel layer and the first and second gate electrodes; a buried insulating layer between the first and second gate electrodes within the trench; and a first contact and a second contact respectively buried in regions adjacent to the opposite sidewalls of the trench in the insulating pattern layer, and respectively connected to upper regions of the channel layer.

2 . The semiconductor device of claim 1 , wherein the conductive line includes a first conductive line and a second conductive line on the first conductive line, and the extension portion of the trench is in the second conductive line.

3 . The semiconductor device of claim 1 , wherein the extension portion of the trench has a depth of 50 nm or less.

4 . The semiconductor device of claim 1 , wherein the channel layer includes first and second vertical channel elements respectively arranged along the opposite sidewalls of the trench, and wherein the channel layer includes a horizontal connection portion that connects the first and second vertical channel elements to each other at a bottom of the trench, the horizontal connection portion connected to the conductive line.

5 . The semiconductor device of claim 4 , wherein each of the first and second vertical channel elements has a lower region in contact with the conductive line and that overlaps the conductive line in a horizontal direction.

6 . The semiconductor device of claim 4 , wherein an upper surface of the conductive line has a level that is farther from the substrate than a lowermost level of the first and second gate electrodes is from the substrate.

7 . The semiconductor device of claim 4 , wherein the gate insulating layer includes a first gate insulating element between the first vertical channel element and the first gate electrode, a second gate insulating element between the second vertical channel element and the second gate electrode, and a bottom insulating layer that connects the first and second gate insulating elements to each other.

8 . The semiconductor device of claim 4 , wherein the first and second vertical channel elements have upper regions that are in contact with the first and second contacts and that overlap the first and second contacts, respectively.

9 . The semiconductor device of claim 1 , wherein the buried insulating layer has an upper surface that is substantially coplanar with upper ends of the first and second gate electrodes, an upper end of the gate insulating layer, and an upper end of the channel layer.

10 . The semiconductor device of claim 1 , wherein the buried insulating layer includes a material that differs from a material of the insulating pattern layer.

11 . The semiconductor device of claim 10 , wherein the buried insulating layer includes an insulating material having an oxygen diffusivity that is lower than an oxygen diffusivity in the material of the insulating pattern layer under equal conditions.

12 . The semiconductor device of claim 1 , wherein the buried insulating layer has a void therein.

13 . A semiconductor device comprising:
a substrate; a plurality of conductive lines that extend on the substrate in a first direction and are spaced apart from each other in a second direction that intersects the first direction; an insulating pattern layer that extends in the second direction on the substrate, the insulating pattern layer having a plurality of trenches spaced apart from each other in the first direction, each trench of the plurality of trenches having a respective extension portion that extends into the plurality of conductive lines; a plurality of channel layers on opposite sidewalls of each of the plurality of trenches and arranged in the second direction, the channel layers connected to regions in the plurality of conductive lines exposed by the extension portions of the plurality of trenches; a plurality of first gate electrodes and a plurality of second gate electrodes on the plurality of channel layers in each of the plurality of trenches and respectively extending on the opposite sidewalls of each of the plurality of trenches; a plurality of gate insulating layers between the plurality of channel layers and the plurality of first and second gate electrodes in each of the plurality of trenches; a plurality of buried insulating portions, respectively within the plurality of trenches, and between the plurality of first and second gate electrodes; and a plurality of first contacts and a plurality of second contacts buried in the insulating pattern layer and connected to upper regions of the plurality of channel layers adjacent to the opposite sidewalls of each of the plurality of trenches.

14 . The semiconductor device of claim 13 , wherein the plurality of channel layers include an oxide semiconductor, and
wherein the buried insulating portions includes an insulating material having an oxygen diffusivity that is lower than an oxygen diffusivity in a material of the insulating pattern layer under equal conditions.

15 . The semiconductor device of claim 13 , further comprising:
a plurality of data storage elements on the insulating pattern layer and electrically connected to the plurality of first and second contacts; and a plurality of interconnection portions connecting respective ones of the plurality of data storage elements with respective ones of the plurality of first and second contacts.

16 . The semiconductor device of claim 15 , wherein the plurality of interconnection portions are respectively arranged on the plurality of first and second contacts and extend to upper ends of adjacent channel layers among the plurality of channel layers.

17 . A semiconductor device comprising:
a substrate; a conductive line extending in a first direction on the substrate; an insulating pattern layer on the substrate and having a trench that extends in a second direction that intersects the first direction; a channel layer arranged on opposite sidewalls of the trench and electrically connected to the conductive line at a bottom of the trench, the channel layer including an oxide semiconductor; a first gate electrode and a second gate electrode respectively on the opposite sidewalls of the trench on the channel layer; a gate insulating layer between the channel layer and the first and second gate electrodes and having a U-shape in a cross-section taken in the second direction; a buried insulating portion between the first and second gate electrodes within the trench, the buried insulating portion including an insulating material that is different from a material of the insulating pattern layer; and a first contact and a second contact electrically connected with respective upper regions of the channel layer, wherein the trench has an extension portion that extends into the conductive line, and wherein the channel la

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Minhee
• Lee Kiseok
• Lee Wonsok
• Ryu Mintae
• Park Hyunmog
• Song Woobin
• Yoo Sungwon

Classifications

• H10D99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/673

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title