Semiconductor device including active region with variable atomic concentration of oxide semiconductor material and method of forming the same

Patent metadata

Field	Value
Publication number	US-10854612-B2
Application number	US-201816185892-A
Country	US
Kind code	B2
Filing date	Nov 9, 2018
Priority date	Mar 21, 2018
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.

First claim

What is claimed:

1. A semiconductor device comprising:
a semiconductor substrate;
an active region on the semiconductor substrate, the active region comprising an oxide semiconductor material having a variable atomic concentration of oxygen;
a first source/drain region in the active region, the first source/drain region having a first atomic concentration of oxygen in the oxide semiconductor material;
a second source/drain region in the active region spaced apart from first source/drain region;
a channel region in the active region between the first source/drain region and the second source/drain region, the channel region having a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen; and
a gate electrode on the channel region and extending between the first source/drain region and the second source/drain region.

2. The semiconductor device of claim 1 , wherein the first atomic concentration of oxygen of the oxide semiconductor material is located at a gate-induced-drain-leakage portion of the first source/drain region.

3. The semiconductor device of claim 1 further comprising a recessed channel array transistor of a dynamic random access memory (DRAM).

4. The semiconductor device of claim 1 , further comprising a planar transistor.

5. The semiconductor device of claim 1 , wherein the oxide semiconductor material comprises InGaZnO and the first atomic concentration of oxygen is about 4.1 and the second atomic concentration of oxygen is about 3.8.

6. The semiconductor device of claim 1 , wherein oxide semiconductor material comprises a single metal and oxygen wherein the single metal comprises a plurality of metals selected from a group consisting of In, Zn, Sn, Al, Mg, Ga, Hf, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

7. The semiconductor device of claim 1 , wherein the gate electrode includes:
a metal gate layer;
a polysilicon high-work function layer on the metal gate layer; and
a gate capping layer on the polysilicon high-work function layer.

8. The semiconductor device of claim 1 , further comprising a finFET semiconductor device,
wherein the active region comprises a fin structure protruding from the semiconductor substrate, and
wherein the gate electrode crosses the fin structure between the first source/drain region and the second source/drain region.

9. The semiconductor device of claim 1 , further comprising a dynamic random access memory (DRAM), wherein the active region comprises a plurality of active regions extending horizontally in a first direction relative to the semiconductor substrate and vertically stacked on one another, each of the plurality of active regions including a respective first source/drain region, a respective second source/drain region, and a respective channel region;
wherein the gate electrode comprises a word line extending vertically from the semiconductor substrate and crossing each of the plurality of active regions between each respective first source/drain region and respective second source/drain region;
a plurality of bit lines extending horizontally in a second direction relative to the semiconductor substrate and vertically stacked on one another, each of the plurality of bit lines crossing a respective second source/drain region; and
a plurality of data storage elements each coupled to a respective first source/drain region.

10. The semiconductor device of claim 1 , further comprising:
a gate electrode in an isolation trench in the active region adjacent to the first source/drain region;
the isolation trench extending through the first atomic concentration of oxygen into the second atomic concentration of oxygen.

11. The semiconductor device of claim 1 , further comprising:
a gate electrode in an isolation trench in the active region adjacent to the first source/drain region, the isolation trench having a side wall covered by the first atomic concentration of oxygen; and
the isolation trench contained within the first atomic concentration of oxygen.

12. A fin field-effect transistor (finFET) semiconductor device comprising:
a semiconductor substrate;
an active fin structure protruding from the semiconductor substrate, the active fin structure comprising InGaZnO having a variable atomic concentration of oxygen ranging from about 3.8 to about 4.1;
a first source/drain region in the active fin structure, the first source/drain region having a first atomic concentration of oxygen in the InGaZnO;
a second source/drain region in the active fin structure spaced apart from first source/drain region;
a channel region in the active fin structure between the first source/drain region and the second source/drain region, the channel region having a second atomic concentration of oxygen in the InGaZnO that is different from the first atomic concentration of oxygen; and
a gate electrode crossing the active fin structure opposite the channel region and extending between the first source/drain region and the second source/drain region.

13. The finFET semiconductor device of claim 12 , wherein the second atomic concentration of oxygen in the InGaZnO that is less than the first atomic concentration of oxygen in the InGaZnO.

14. The finFET semiconductor device of claim 12 , wherein the second atomic concentration of oxygen in the InGaZnO that is greater than the first atomic concentration of oxygen in the InGaZnO.

15. The finFET semiconductor device of claim 12 , wherein the gate electrode includes:
a metal gate layer;
a polysilicon high-work function layer on the metal gate layer; and
a gate capping layer on the polysilicon high-work function layer.

16. A semiconductor device comprising:
a semiconductor substrate;
an active region on the semiconductor substrate, the active region comprising InGaZnO having a variable atomic concentration of oxygen;
a first source/drain region in the active region, the first source/drain region having a first atomic concentration of oxygen in the InGaZnO;
a second source/drain region in the active region spaced apart from first source/drain region;
a channel region in the active region between the first source/drain region and the second source/drain region, the channel region having a second atomic concentration of oxygen in the InGaZnO that is different from the first atomic concentration of oxygen; and
a gate electrode on the channel region and extending between the first source/drain region and the second source/drain region.

17. The semiconductor device of claim 16 , wherein the first atomic concentration of oxygen in the InGaZnO is located at a gate-induced-drain-leakage portion of the first source/drain region.

18. The semiconductor device of claim 16 , wherein the gate electrode comprises:
a metal gate layer;
a polysilicon high-work function layer on the metal gate layer; and
a gate capping layer on the polysilicon high-work function layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Minhee
• Kim Junsoo
• Lee Ho
• Kim Chankyung
• Kim Hei Seung
• Min Jaehong
• Park Sangwuk
• Song Woo Bin
• Lee Sang Woo

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10P10/00 Primary

  Bonding of wafers, substrates or parts of devices · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title