Transistors including heterogeneous channels, and related devices, memory devices, electronic systems, and methods

Patent metadata

Field	Value
Publication number	US-2020111908-A1
Application number	US-201916596448-A
Country	US
Kind code	A1
Filing date	Oct 8, 2019
Priority date	Oct 9, 2018
Publication date	Apr 9, 2020
Grant date	—

Abstract

A transistor comprises a first conductive contact, a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact, a second conductive contact over the heterogeneous channel, and a gate electrode laterally neighboring the heterogeneous channel. A device, a method of forming a device, a memory device, and an electronic system are also described.

First claim

What is claimed is:

1 . A transistor, comprising:
a first conductive contact; a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact; a second conductive contact over the heterogeneous channel; and a gate electrode laterally neighboring the heterogeneous channel.

2 . The transistor of claim 1 , wherein the heterogeneous channel comprises:
a lower region directly contacting the first conductive contact; an upper region directly contacting the second conductive contact; and a middle region vertically between the lower region and the upper region, the middle region having one or more of a decreased atomic concentration of at least one metal, a decreased atomic concentration of at least one metalloid, and an increased atomic concentration of oxygen relative to the lower region and the upper region.

3 . The transistor of claim 2 , wherein:
the middle region comprises a first oxide semiconductor material; and one or more of the lower region and the upper region comprises a second oxide semiconductor material having a different material composition than the first oxide semiconductor material.

4 . The transistor of claim 2 , wherein the lower region, the middle region, and the upper region each comprise substantially the same elements as one another.

5 . The transistor of claim 2 , wherein the lower region, the middle region, and the upper region are each substantially homogeneous.

6 . The transistor of claim 2 , wherein one or more of the lower region and the upper region is heterogeneous.

7 . The transistor of claim 6 , wherein amounts of one or more of at least one metal and at least one metalloid in the lower region and the upper region increase in directions extending vertically away from the middle region.

8 . The transistor of claim 2 , wherein one or more of the lower region and the upper region is doped with at least one element selected from hydrogen, nitrogen, phosphorus, boron, arsenic, and tellurium.

9 . The transistor of claim 1 , further comprising another gate electrode, the gate electrode and the another gate electrode laterally neighboring different sides of the heterogeneous channel than one another.

10 . The transistor of claim 1 , wherein the gate electrode laterally surrounds all lateral boundaries heterogeneous channel.

11 . The transistor of claim 1 , wherein the heterogeneous channel comprises:
a lower region; an upper region; and a middle region vertically between the lower region and the upper region, the lower region and the upper region each exhibiting a lower band gap than the middle region.

12 . The transistor of claim 11 , wherein the lower region and the upper region have increased atomic concentration of indium the relative to middle region.

13 . A device, comprising:
a conductive line; a conductive contact on the conductive line; pillar structures on the conductive contact, each pillar structure comprising:
an oxide semiconductor channel comprising a region and at least one additional region, the region having one or more of a different material composition and a different atomic concentration of one or more elements than at least one additional region; and
another conductive contact on the oxide semiconductor channel;
gate electrodes laterally neighboring the pillar structures; and dielectric material intervening between the gate electrodes and the pillar structures.

14 . The device of claim 13 , wherein the region of the oxide semiconductor channel is oxygen-rich relative to the at least one additional region.

15 . The device of claim 13 , wherein the at least one additional region of the oxide semiconductor channel is metal-rich relative to the region.

16 . The device of claim 13 , wherein the at least one additional region of the oxide semiconductor channel is relatively oxygen-rich and metal-lean proximate the region, and is relatively oxygen-lean and metal-rich distal from the region.

17 . The device of claim 13 , wherein the region of the oxide semiconductor channel comprises In x Ga y Zn z O, and the at least one additional region of the oxide semiconductor channel comprises In x O.

18 . The device of claim 13 , wherein the oxide semiconductor channel comprises one or more of Zn x Sn y O, In x Zn y O, Zn x O, In x Ga y Zn z O, In x Ga y Si z O a , In x W y O, In x O, Sn x O, Ti x O, Zn x ON z , Mg x Zn y O, Zr x In y Zn z O, Hf x In y Zn z O, Sn x In y Zn z O, Al x Sn y In z Zn a O, Si x In y Zn z O, Al x Zn y Sn z O, Ga x Zn y Sn z O, Zr x Zn y Sn z O, and In x Ga y Si z O.

19 . A method of forming a device, comprising:
forming a heterogeneous channel material on a conductive structure, the heterogeneous channel material comprising at least one oxide semiconductor material; forming a conductive material on the heterogeneous channel material; removing portions of the conductive material and the heterogeneous channel material to form pillar structures laterally separated from one another by openings; and forming electrode structures and dielectric liner structures in the openings.

20 . The method of claim 19 , wherein forming a heterogeneous channel material comprises forming the heterogeneous channel material to comprise a lower region, a middle region, and an upper region, the middle region having a larger band gap than each of the lower region and the upper region.

21 . The method of claim 20 , wherein forming the heterogeneous channel material comprises forming the middle region to have a greater atomic concentration of oxygen than each of the lower region and the upper region.

22 . The method of claim 20 , wherein forming the heterogeneous channel material comprises forming the heterogeneous channel material through a PVD process that includes manipulating one or more of oxygen flow and plasma bombardment parameters during deposition of the lower region, the middle region, and the upper region of the heterogeneous channel material.

23 . The method of claim 20 , wherein manipulating one or more of oxygen flow and plasma bombardment parameters during deposition of the lower region, the middle region, and the upper region of the heterogeneous channel material comprises employing a different power to form to the middle region using plasma bombardment of a target that that used to form one or more of the lower region and the upper region using plasma bombardment of at least one target.

24 . The method of claim 20 , wherein forming the heterogeneous channel material comprises forming the heterogeneous channel material through one or more of an ALD process and a CVD process that includes manipulating one or more of precursor species, precursor species amounts, precursor pulse times, reactant species, reactant species amounts, reactant pulse times, inert species, and inert species pulse times during deposition of the lower region, the middle region, and the upper region of the heterogeneous channel material.

25 . The method of claim 20 , wherein forming the heterogeneous channel material comprises doping one or more of the lower region and the upper region with one or more of hydrogen, deuterium, nitrogen, phosphorus, and arsenic.

26 . The method of claim 20 , wherein forming the heterogeneous channel material comprises forming the lower region and the upper region to have substantially the same band gap as one another.

Assignees

• Micron Technology Inc

Inventors

• Sills Scott E
• Gandhi Ramanathan
• Ramaswamy Durai Vishak Nirmal
• Lee Yi Fang
• Karda Kamal M

Classifications

• H01L27/2454

  Electricity · mapped topic

• H01L29/1054

  Electricity · mapped topic

• H01L29/7827 Primary

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic

• H10W70/65

  Shapes or dispositions of interconnections · CPC title