Method for fabricating semiconductor device having multiple threshold voltages

Patent metadata

Field	Value
Publication number	US-9177865-B2
Application number	US-201414271909-A
Country	US
Kind code	B2
Filing date	May 7, 2014
Priority date	Jun 5, 2013
Publication date	Nov 3, 2015
Grant date	Nov 3, 2015

Abstract

Provided are methods for fabricating a semiconductor device. A gate dielectric layer is formed on a substrate including first through third regions. A first functional layer is formed on only the first region of the first through third regions. A second functional layer is formed on only the first and second regions of the first through third regions. A threshold voltage adjustment layer is formed on the first through third regions. The threshold voltage adjustment layer includes a work function adjustment material. The work function adjustment material is diffused into the gate dielectric layer by performing a heat treatment process with respect to the substrate.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device comprising:
forming a gate dielectric layer on a substrate including first through third regions;
forming a first functional layer on only the first region of the first through third regions;
forming a second functional layer on only the first and second regions of the first through third regions;
forming a threshold voltage adjustment layer on the first through third regions, the threshold voltage adjustment layer including a work function adjustment material; and
diffusing the work function adjustment material into the gate dielectric layer by performing a heat treatment process with respect to the substrate.

2. The method for fabricating a semiconductor device of claim 1 , wherein an amount of the work function adjustment material, which is diffused into the gate dielectric layer of the first through third regions, differs at each of the first through third regions.

3. The method for fabricating a semiconductor device of claim 2 , wherein the amount of the work function adjustment material that is diffused into the gate dielectric layer of the first region is smaller than the amount of the work function adjustment material that is diffused into the gate dielectric layer of the second region, and wherein the amount of the work function adjustment material that is diffused into the gate dielectric layer of the second region is smaller than the amount of the work function adjustment material that is diffused into the gate dielectric layer of the third region.

4. The method for fabricating a semiconductor device of claim 1 , wherein the substrate further comprises a fourth region, wherein forming a second functional layer on only the first and second regions includes forming the first functional layer and an etch prevention layer on only the first and fourth regions, and wherein forming the threshold voltage adjustment layer that includes the work function adjustment material on the first through third regions includes forming the threshold voltage adjustment layer that includes the work function material on the first through fourth regions.

5. The method for fabricating a semiconductor device of claim 4 , wherein the first functional layer comprises the work function adjustment material.

6. The method for fabricating a semiconductor device of claim 4 , wherein at least one of the first functional layer, the second functional layer, or the etch prevention layer comprise at least one of Ti, Ta, and Si, a nitride thereof, an alloy thereof, or a stacked structure thereof.

7. The method for fabricating a semiconductor device of claim 6 , wherein the first functional layer and the second functional layer each comprises TiN.

8. The method for fabricating a semiconductor device of claim 6 , wherein the etch prevention layer comprises TaN.

9. The method for fabricating a semiconductor device of claim 1 , wherein the work function adjustment material comprises at least one of lanthanide materials, a nitride thereof, or an alloy thereof.

10. The method for fabricating a semiconductor device of claim 9 , wherein the work function adjustment material comprises La.

11. The method for fabricating a semiconductor device of claim 1 , wherein forming the gate dielectric layer comprises:
forming an interface film on the substrate; and
forming a gate insulating film having high-k on the interface film.

12. The method for fabricating a semiconductor device of claim 1 , wherein the substrate comprises an nFET region and a pFET region, and wherein the method further comprises forming an n-type metal gate on the nFET region and forming a p-type metal gate on the pFET region.

13. The method for fabricating a semiconductor device of claim 12 , wherein forming the n-type metal gate on the nFET region and forming the p-type metal gate on the pFET region comprises:
forming a p-type work function metal layer on the nFET region and the pFET region of the substrate;
removing the p-type work function metal layer from the nFET region of the substrate; and
forming the n-type work function metal layer on the nFET region of the substrate.

14. The method for fabricating a semiconductor device of claim 12 , wherein the n-type metal gate includes at least one of Al, Ta, Mo, Zr, Hf, V, Ti, a nitride thereof, an alloy thereof, and a stacked structure thereof, and
the p-type metal gate includes at least one of Co, Pd, Ni, Re, Ir, Ru, Ti, a nitride thereof, an alloy thereof, and a stacked structure thereof.

15. A method for fabricating a semiconductor device comprising:
forming a gate dielectric layer on a substrate including first and second regions;
forming a first threshold voltage adjustment layer on only the first region, the first threshold voltage adjustment layer including a work function adjustment material;
forming an etch prevention layer on the first and second regions;
forming a block layer on only the etch prevention layer of the second region;
forming a second threshold voltage adjustment layer that includes the work function adjustment material on the first and second regions so that the block layer is formed between the etch prevention layer and the second threshold adjustment layer in the second region; and
diffusing the work function adjustment material into the gate dielectric layer by performing a heat treatment process with respect to the substrate.

16. The method for fabricating a semiconductor device of claim 15 , wherein an amount of the work function adjustment material diffused into the gate dielectric layer of the first and second regions differs at each of the first and second regions.

17. The method for fabricating a semiconductor device of claim 16 , wherein the amount of the work function adjustment material that is diffused into the gate dielectric layer of the second region is smaller than the amount of the work function adjustment material that is diffused into the gate dielectric layer of the first region.

18. The method for fabricating a semiconductor device of claim 16 , wherein the block layer comprises at least one of Ti, Ta, and Si, a nitride thereof, an alloy thereof, or a stacked structure thereof.

19. A method for fabricating a semiconductor device comprising:
forming a gate dielectric layer on a substrate, the gate dielectric layer including a first region, a second region, and a third region, each of the first through third regions constructed and arranged for different threshold voltages;
forming a first functional layer on the first region;
forming a second functional layer on the first and second regions;
forming a threshold voltage adjustment layer on the first through third regions, the threshold voltage adjustment layer including a work function adjustment material; and
diffusing the work function adjustment material into the gate dielectric layer, wherein a thickness of the semiconductor device from the threshold voltage adjustment layer to the gate dielectric layer is different at each of the first through third regions, wherein the amount of the work function adjustment material diffused into the gate dielectric layer is different at each of the first through third regions, and wherein the threshold voltages at the first through third regions, respectively, are dependent on the amounts of the work function adjustment material diffused into the gate dielectric layer at the first through respectively.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Woo-Hee
• Lee Nae-In
• Kim Kug-Hwan
• Lee Jong-Ho

Classifications

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D84/0181

  Manufacturing their gate insulating layers · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title

• H10D84/0144 Primary

  Manufacturing their gate insulating layers · CPC title