Semiconductor device including barrier layer between active region and semiconductor layer and method of forming the same

Patent metadata

Field	Value
Publication number	US-12453141-B2
Application number	US-202418658794-A
Country	US
Kind code	B2
Filing date	May 8, 2024
Priority date	May 24, 2019
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
an active region on the substrate;
an isolation region on the substrate and on side surfaces of the active region;
a first source/drain region and a second source/drain region on the active region and spaced apart from each other;
a barrier layer on and physically contacting the active region;
a lower semiconductor layer on and physically contacting the barrier layer;
upper semiconductor layers on the lower semiconductor layer and spaced apart from each other in a vertical direction; and
a gate structure covering an upper surface, a lower surface, and side surfaces of each of the upper semiconductor layers in a first direction and extending on the isolation region,
wherein the vertical direction is perpendicular to an upper surface of the substrate,
wherein the first direction is parallel to the upper surface of the substrate,
wherein a material of the barrier layer is different from a material of the upper semiconductor layers and a material of the lower semiconductor layer, and
wherein the upper semiconductor layers, the lower semiconductor layer, and at least a portion of the barrier layer are between the first source/drain region and the second source/drain region.

2. The semiconductor device of claim 1 , wherein lower surfaces of the first source/drain region and the second source/drain region physically contact the active region.

3. The semiconductor device of claim 1 , wherein lower surfaces of the first source/drain region and the second source/drain region are at a lower level than a lower surface of the barrier layer.

4. The semiconductor device of claim 1 , wherein a lower surface of the barrier layer is at a lower level than a lower surface of the gate structure adjacent to a side surface of the barrier layer.

5. The semiconductor device of claim 1 , wherein a lower surface of the barrier layer is at a higher level than a lower surface of the gate structure adjacent to a side surface of the barrier layer.

6. The semiconductor device of claim 1 , wherein the barrier layer includes a barrier impurity element, and
wherein the upper semiconductor layers and the lower semiconductor layer do not include the barrier impurity element.

7. The semiconductor device of claim 1 , wherein a thickness of the lower semiconductor layer is different from a thickness of at least one of the upper semiconductor layers.

8. The semiconductor device of claim 1 , wherein the lower semiconductor layer physically contacts an upper surface of the barrier layer.

9. The semiconductor device of claim 1 , wherein the lower semiconductor layer and the upper semiconductor layers are configured as channels.

10. The semiconductor device of claim 1 , wherein the lower semiconductor layer and the barrier layer have a same width in a second direction perpendicular to the vertical direction and the first direction.

11. The semiconductor device of claim 1 , wherein the barrier layer is doped with oxygen.

12. The semiconductor device of claim 11 , wherein a concentration of oxygen in the barrier layer is in a range from 10 15 atoms/cm 3 to 10 22 atoms/cm 3 .

13. The semiconductor device of claim 1 , wherein the barrier layer is doped with an impurity element, and wherein a concentration of the impurity element in a lower region of the barrier layer is higher than a concentration of the impurity element in an upper region of the barrier layer.

14. A semiconductor device, comprising:
an active region;
an isolation region on side surfaces of the active region;
a first source/drain region and a second source/drain region on the active region and spaced apart from each other;
a barrier layer on and physically contacting the active region;
a lower semiconductor layer on and physically contacting the barrier layer;
upper semiconductor layers on the lower semiconductor layer and spaced apart from each other in a vertical direction; and
a gate structure covering an upper surface, a lower surface, and side surfaces of each of the upper semiconductor layers in a first direction and extending on the isolation region,
wherein the vertical direction is perpendicular to the first direction,
wherein a material of the barrier layer is different from a material of the upper semiconductor layers and a material of the lower semiconductor layer, and
wherein the upper semiconductor layers, the lower semiconductor layer, and at least a portion of the barrier layer are between the first source/drain region and the second source/drain region.

15. The semiconductor device of claim 14 , wherein lower surfaces of the first source/drain region and the second source/drain region physically contact the active region.

16. The semiconductor device of claim 14 , wherein lower surfaces of the first source/drain region and the second source/drain region are at a lower level than a lower surface of the barrier layer.

17. The semiconductor device of claim 14 , wherein a thickness of the lower semiconductor layer is different from a thickness of at least one of the upper semiconductor layers.

18. A semiconductor device, comprising:
a first source/drain region and a second source/drain region spaced apart from each other;
an active region including a portion between the first source/drain region and the second source/drain region;
a barrier layer on and physically contacting the active region;
a lower semiconductor layer on and physically contacting the barrier layer;
upper semiconductor layers on the lower semiconductor layer and spaced apart from each other in a vertical direction; and
a gate structure covering an upper surface, a lower surface, and side surfaces of each of the upper semiconductor layers in a first direction,
wherein the vertical direction is perpendicular to the first direction,
wherein a material of the barrier layer is different from a material of the upper semiconductor layers and a material of the lower semiconductor layer, and
wherein the upper semiconductor layers, the lower semiconductor layer, the barrier layer, and the portion of the active region are between the first source/drain region and the second source/drain region.

19. The semiconductor device of claim 18 , wherein a thickness of the lower semiconductor layer is different from a thickness of at least one of the upper semiconductor layers.

20. The semiconductor device of claim 18 , wherein the active region is in physical contact with the first source/drain region and the second source/drain region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Sungkeun
• Kim Unki
• Jo Yuyeong
• Kim Yihwan
• Kim Jinbum
• Park Pankwi
• Shin Ilgyou
• Lee Seunghun

Classifications

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title