Field effect transistor having germanium nanorod and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9318573-B2
Application number	US-201313973584-A
Country	US
Kind code	B2
Filing date	Aug 22, 2013
Priority date	May 3, 2007
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate insulation layer formed on a silicon substrate, at least one nanorod embedded in the gate insulation layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate insulation layer between the source electrode and the drain electrode.

First claim

What is claimed is:

1. A method of manufacturing a field effect transistor, the method comprising:
forming an insulating layer and a first silicon layer on a silicon substrate;
sequentially forming at least two alternating SiGe layers and second silicon layers on the first silicon layer after the forming an insulating layer and a first silicon layer;
forming silicon oxide layers by oxidizing the first and second silicon layers and Si of the at least two SiGe layers on the silicon substrate, and forming at least two Ge nanorods from the at least two SiGe layers;
forming a source electrode on one end of each of the at least two Ge nanorods, the one end of the at least two Ge nanorods being embedded in the source electrode;
forming a drain electrode on another end of each of the at least two Ge nanorods, the one end of the at least two Ge nanorods being embedded in the drain electrode;
forming a gate insulation layer that surrounds the at least two Ge nanorods in a region for forming a channel region between the source electrode and the drain electrode; and
forming a gate electrode on the gate insulation layer.

2. The method of claim 1 , wherein the sequentially forming of the at least two alternating SiGe layers and the second silicon layers includes forming from 2 to 5 SiGe layers separated by the second silicon layers on the first silicon layer.

3. The method of claim 1 , wherein the insulating layer is formed of a material having an etching rate different from that of the silicon oxide layers.

4. The method of claim 1 , wherein forming the source electrode and the drain electrode comprises:
forming a first photoresist in the region for forming the channel region;
exposing both ends of the at least two Ge nanorods by removing the silicon oxide layers in regions for forming the source electrode and the drain electrode; and
depositing a metal having a work function greater than that of Ge in the regions for forming the source electrode and the drain electrode.

5. The method of claim 1 , wherein forming the gate insulation layer comprises:
exposing the at least two Ge nanorods by removing the silicon oxide layers in the region for forming the channel region; and
forming the gate insulation layer that surrounds the at least two Ge nanorods using a material having a dielectric constant higher than that of silicon oxide.

6. The method of claim 5 , further comprising:
forming a cross-section of each of the at least two Ge nanorods in the channel region into a circle or an oval shape by annealing the silicon substrate at least two Ge nanorods in a H 2 or D 2 atmosphere prior to forming the gate insulation layer.

7. The method of claim 5 , wherein the material is one selected from the group consisting of Si 3 N 4 , Ta 2 O 5 , HfO 2 , Zr 2 O 5 , Al 2 O 3 , HfO x N y , HfSiO, and HfSiON.

8. The method of claim 7 , wherein the forming of the gate electrode comprises forming a first conductive layer formed of one selected from Ta, TaN, and TiN and forming a second conductive layer formed of polysilicon on the first conductive layer.

9. The method of claim 1 , wherein each of the at least two SiGe layers has a composition of Si 1-x Ge, where 0.1<x<0.5.

10. The method of claim 1 , wherein the source electrode and the drain electrode are formed of a metal selected from the group consisting of Pt, Ni, Co, V, Yb, and Er.

11. The method of claim 1 , wherein the gate insulation layer is formed of silicon oxide, and the forming of the gate electrode comprises forming a polysilicon layer.

12. The method of claim 1 , wherein the at least two Ge nanorods have a diameter of about 1 to about 20 nm.

13. The method of claim 1 , wherein the first silicon layer, the at least two alternating SiGe layers and the second silicon layers are formed overlapping the insulating layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Moon Chang-Wook
• Jeon Joong S
• Lee Jung-Hyun
• Lee Nae-In
• Park Yeon-Sik
• Rhee Hwa-Sung
• Lee Ho
• Cho Se-Young
• Kim Suk-Pil

Classifications

• H10P14/6544

  to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer · CPC title

• H10P14/3461

  Nanoparticles · CPC title

• H10P14/20

  of semiconductor materials · CPC title

• H10W20/0554

  of nanotubes or nanowires · CPC title

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title