Semiconductor structure with dopants diffuse protection and method for forming the same

Patent metadata

Field	Value
Publication number	US-9899273-B1
Application number	US-201615379983-A
Country	US
Kind code	B1
Filing date	Dec 15, 2016
Priority date	Dec 15, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Semiconductor structures and methods for forming the same are provided. The method for forming a semiconductor structure includes forming an N-well region in a substrate and forming a first protection layer over the N-well region. The method for forming a semiconductor structure further includes forming a P-well region in the substrate and forming a second protection layer over the P-well region. The method for forming a semiconductor structure further includes growing a first channel layer over the first protection layer and a second channel layer over the second protection layer and forming a first gate structure over the first channel layer and a second gate structure over the second channel layer.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, comprising:
forming an N-well region in a substrate;
forming a first protection layer over the N-well region;
forming a P-well region in the substrate;
forming a second protection layer over the P-well region;
growing a first channel layer over the first protection layer;
growing a second channel layer over the second protection layer;
forming a first gate structure over the first channel layer;
forming a second gate structure over the second channel layer;
forming a first source/drain structure in the first channel layer; and
forming a second source/drain structure in the second channel layer,
wherein the first source/drain structure has a thickness substantially equal to the thickness of the first channel layer, and the second source/drain structure has a thickness substantially equal to the thickness of the second channel layer.

2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the first protection layer and the second protection layer are formed by doping dopants in the substrate.

3. The method for forming a semiconductor structure as claimed in claim 2 , wherein the dopants comprise carbon and/or nitrogen.

4. The method for forming a semiconductor structure as claimed in claim 1 , wherein the first channel layer is formed by performing an epitaxial growth process.

5. The method for forming a semiconductor structure as claimed in claim 1 , wherein the first channel layer has a thickness greater than that of the second channel layer.

6. The method for forming a semiconductor structure as claimed in claim 1 , wherein a bottom surface of the first gate structure is higher than that of the second gate structure.

7. The method for forming a semiconductor structure as claimed in claim 1 , wherein a top surface of the first channel layer is higher than a top surface of the second channel layer.

8. A method for forming a semiconductor structure, comprising:
forming an N-well region in a substrate;
forming a first protection layer over the N-well region by performing a first implanting process;
forming a P-well region in the substrate;
forming a second protection layer over the P-well region by performing a second implanting processes;
forming a first channel layer over the first protection layer;
forming a second channel layer over the second protection layer;
forming a first gate structure over the first channel layer;
forming a second gate structure over the second channel layer; and
forming a first source/drain structure in the first channel layer,
wherein a bottommost portion of the first source/drain structure is higher than a bottom surface of the first protection layer.

9. The method for forming a semiconductor structure as claimed in claim 8 , wherein same dopants are used in the first implanting process and the second implanting process.

10. The method for forming a semiconductor structure as claimed in claim 8 , wherein the first channel layer and the second channel layer are formed by performing epitaxial growth processes.

11. The method for forming a semiconductor structure as claimed in claim 10 , wherein a thickness of the first channel layer is greater than a thickness of the second channel layer.

12. The method for forming a semiconductor structure as claimed in claim 10 , further comprising:
forming a second source/drain structure in the second channel layer,
wherein the first source/drain structure is in contact with the first protection layer, and the second source/drain structure is in contact with the second protection layer.

13. The method for forming a semiconductor structure as claimed in claim 8 , further comprising:
forming a second source/drain structure in the second channel layer,
wherein a bottommost portion of the second source/drain structure is higher than a bottom surface of the second protection layer, and the bottom surface of the second protection layer is higher than the bottommost portion of the first source/drain structure.

14. A semiconductor structure, comprising:
a substrate;
an N-well region and a P-well region formed in the substrate;
a first protection layer formed over the N-well region;
a second protection layer formed over the P-well region;
a first channel layer formed over the first protection layer;
a second channel layer formed over the second protection layer;
a first gate structure formed over the first channel layer; and
a second gate structure formed over the second channel layer,
wherein a thickness of the first channel layer is greater than a thickness of the second channel layer.

15. The semiconductor structure as claimed in claim 14 , wherein the first protection layer and the second protection layer comprise the same dopants.

16. The semiconductor structure as claimed in claim 15 , wherein the dopants comprises carbon and/or nitrogen.

17. The semiconductor structure as claimed in claim 14 , further comprising:
a first source/drain structure formed in the first channel layer; and
a second source/drain structure formed in the second channel layer,
wherein a thickness of the first source/drain structure is substantially equal to the thickness of the first channel layer, and a thickness of the second source/drain structure is substantially the equal to the thickness of the second channel layer.

18. The semiconductor structure as claimed in claim 14 , wherein a difference between the thickness of the first channel layer and the thickness of the second channel region is in a range from about 10 nm to about 30 nm.

19. The semiconductor structure as claimed in claim 14 , wherein a top surface of the first channel layer is higher than a top surface of the second channel layer.

20. The semiconductor structure as claimed in claim 14 , wherein a thickness of the first protection layer is in a range from about 5 nm to about 25 nm.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Chun Chieh
• Huang yi min
• Yang Huai Tei
• Chang Shih Chieh
• Pan zheng yang

Classifications

• H01L27/0928

  Electricity · mapped topic

• H01L21/82385

  Electricity · mapped topic

• H01L21/823892 Primary

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic

• H01L21/265

  Electricity · mapped topic