Semiconductor device having germanium active layer with underlying diffusion barrier layer

Patent metadata

Field	Value
Publication number	US-10186580-B2
Application number	US-201715433441-A
Country	US
Kind code	B2
Filing date	Feb 15, 2017
Priority date	Dec 23, 2011
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.

First claim

What is claimed is:

1. A semiconductor device, comprising:
one or more germanium nanowires disposed above a substrate;
a junction leakage suppression layer disposed above the substrate, below the one or more germanium nanowires
a gate electrode stack disposed on the leakage suppression layer and completely surrounding at least a portion of each of the one or more germanium nanowires;
spacers disposed adjacent the gate electrode stack and over a fin structure comprising one or more layers of germanium and one or more layers of a second different semiconductor material;
a diffusion barrier layer disposed on the leakage suppression layer, below the spacers; and
source and drain regions disposed on the junction leakage suppression layer, on either side of the spacers of the gate electrode stack.

2. The semiconductor device of claim 1 , wherein the one or more germanium nanowires includes two or more germanium nanowires, the two or more germanium nanowires arranged in a vertically-aligned stack.

3. The semiconductor device of claim 1 , further comprising:
a grading stack disposed directly between the substrate and the junction leakage suppression layer.

4. The semiconductor device of claim 1 , wherein the one or more germanium nanowires consist essentially of germanium, and the junction leakage suppression layer comprises phosphorous doped silicon germanium having a germanium to silicon ratio Si 1-y Ge y .

5. The semiconductor device of claim 4 , wherein the diffusion barrier layer comprises silicon germanium having a germanium to silicon ratio Si 1-x Ge x .

6. The semiconductor device of claim 5 , wherein the diffusion barrier layer comprises silicon germanium having a germanium to silicon ratio Si 1-x Ge x , where x is at least an order of magnitude less than y.

7. The semiconductor device of claim 4 , wherein the diffusion barrier layer consists essentially of silicon.

8. The semiconductor device of claim 1 , wherein the diffusion barrier layer is tensily stressed, and the one or more germanium nanowires are compressively stressed.

9. The semiconductor device of claim 1 , wherein the source and drain regions are embedded source and drain regions.

10. The semiconductor device of claim 9 , wherein the embedded source and drain regions are epitaxial source and drain regions comprising a semiconductor material different from the one or more germanium nanowires.

11. The semiconductor device of claim 1 , wherein the source and drain regions comprise portions of the one or more germanium nanowires.

12. An integrated circuit structure, comprising:
a plurality of germanium nanowires arranged in a vertically-aligned stack above a substrate;
a junction leakage suppression layer disposed above the substrate, below the plurality of germanium nanowires;
a gate electrode stack disposed on the leakage suppression layer and completely surrounding at least a portion of each of the plurality of germanium nanowires;
a pair of insulating spacers on either side of the gate electrode stack and over a fin structure comprising alternating layers of germanium and a second different semiconductor material; and
source and drain regions disposed on the junction leakage suppression layer, on either side of the pair of insulating spacers.

13. The integrated circuit structure of claim 12 , further comprising:
a grading stack disposed directly between the substrate and the junction leakage suppression layer.

14. The integrated circuit structure of claim 12 , wherein each of the plurality of germanium nanowires consist essentially of germanium, and the junction leakage suppression layer comprises phosphorous doped silicon germanium having a germanium to silicon ratio Si 1-y Ge y .

15. The integrated circuit structure of claim 12 , wherein the source and drain regions are embedded source and drain regions.

16. The integrated circuit structure of claim 15 , wherein the embedded source and drain regions are epitaxial source and drain regions comprising a semiconductor material different from the plurality of germanium nanowires.

17. The integrated circuit structure of claim 12 , wherein the source and drain regions comprise portions of the plurality of germanium nanowires.

18. An integrated circuit structure, comprising:
a germanium nanowire above a substrate;
a junction leakage suppression layer disposed above the substrate, below the germanium nanowire;
a gate electrode stack disposed on the leakage suppression layer and completely surrounding a channel region of the germanium nanowire;
spacers disposed adjacent the gate electrode stack and over a fin structure comprising a layer of germanium and a layer of a second different semiconductor material;
a diffusion barrier layer disposed on the leakage suppression layer, below the spacers; and
source and drain regions disposed on the junction leakage suppression layer, on either side of the spacers of the gate electrode stack.

19. The integrated circuit structure of claim 18 , wherein the source and drain regions are embedded source and drain regions.

20. The integrated circuit structure of claim 19 , wherein the embedded source and drain regions are epitaxial source and drain regions comprising a semiconductor material different from the germanium nanowire.

21. The integrated circuit structure of claim 18 , further comprising:
a grading stack disposed directly between the substrate and the junction leakage suppression layer.

22. The integrated circuit structure of claim 18 , wherein the germanium nanowire consists essentially of germanium, and the junction leakage suppression layer comprises phosphorous doped silicon germanium having a germanium to silicon ratio Si 1-y Ge y .

23. The integrated circuit structure of claim 22 , wherein the diffusion barrier layer comprises silicon germanium having a germanium to silicon ratio Si 1-x Ge x , where x is less than y.

24. The semiconductor device of claim 22 , wherein the diffusion barrier layer consists essentially of silicon.

25. The integrated circuit structure of claim 18 , wherein the diffusion barrier layer is tensily stressed, and the germanium nanowire is compressively stressed.

Assignees

• Intel Corp

Inventors

• Rachmady Willy
• Le Van H
• Pillarisetty Ravi
• Kavalieros Jack T
• Chau Robert S
• Kennel Harold W

Classifications

• H10D64/01356 Primary

  the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence) · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/775

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L29/1054

  Electricity · mapped topic