Semiconductor device

Patent metadata

Field	Value
Publication number	US-10243040-B1
Application number	US-201815964170-A
Country	US
Kind code	B1
Filing date	Apr 27, 2018
Priority date	Oct 18, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A semiconductor device including a transistor disposed on a first region of a substrate, the transistor including source/drain regions, a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate while connecting the source/drain regions, respectively, a gate electrode surrounding each of the plurality of channel layers, and a gate insulator between the gate electrode and the plurality of channel layers; and a non-active component disposed on a second region of the substrate, the non-active component including a fin structure including an a plurality of first semiconductor patterns alternately stacked with a plurality of second semiconductor patterns, an epitaxial region adjacent to the fin structure, a non-active electrode intersecting the fin structure, and a blocking insulation film between the non-active electrode and the fin structure.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a transistor disposed on a first region of a substrate, the transistor including:
source/drain regions,
a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate while connecting the source/drain regions, respectively,
a gate electrode surrounding each of the plurality of channel layers, and
a gate insulator between the gate electrode and the plurality of channel layers; and

a non-active component disposed on a second region of the substrate, the non-active component including:
a fin structure including a plurality of first semiconductor patterns alternately stacked with a plurality of second semiconductor patterns,
an epitaxial region adjacent to the fin structure,
a non-active electrode intersecting the fin structure, and
a blocking insulation film between the non-active electrode and the fin structure.

2. The semiconductor device as claimed in claim 1 , wherein the blocking insulation film includes silicon nitride or silicon oxynitride.

3. The semiconductor device as claimed in claim 2 , wherein the blocking insulation film includes a first film including silicon oxide and a second film including silicon nitride.

4. The semiconductor device as claimed in claim 1 , wherein the plurality of second semiconductor patterns are located at a same level as respective ones of the plurality of channel layers.

5. The semiconductor device as claimed in claim 1 , wherein the plurality of second semiconductor patterns and the plurality of channel layers include a same semiconductor material.

6. The semiconductor device as claimed in claim 1 , wherein the non-active electrode and the gate electrode include a same electrode material.

7. The semiconductor device as claimed in claim 1 , wherein the plurality of first semiconductor patterns and the epitaxial region include a same semiconductor material.

8. The semiconductor device as claimed in claim 1 , wherein the epitaxial region includes a same semiconductor epitaxial portion as the source/drain regions.

9. The semiconductor device as claimed in claim 8 , wherein the epitaxial region includes silicon germanium (SiGe).

10. The semiconductor device as claimed in claim 1 , wherein:
the first region of the substrate includes an N-well,
the second region of the substrate includes a P-well, and
the transistor is a P-channel metal oxide semiconductor (P-MOS) transistor.

11. The semiconductor device as claimed in claim 1 , further comprising a contact plug connected to the epitaxial region.

12. The semiconductor device as claimed in claim 1 , wherein the non-active component is a portion of a bipolar transistor or a power supply tap.

13. A semiconductor device, comprising:
a transistor on a first region of a substrate, the transistor including:
source/drain regions arranged in a first direction,
a plurality of channel layers arranged in a direction perpendicular to an upper surface of the substrate and spaced apart from each other while connecting the source/drain regions,
a gate electrode extending in a second direction, intersecting the first direction, while surrounding the plurality of channel layers, and
a gate insulator between the gate electrode and the plurality of channel layers;

a non-active component on a second region of the substrate, the non-active component including:
a fin structure including a plurality of first semiconductor patterns alternately stacked with a plurality of second semiconductor patterns,
an epitaxial region disposed in the first direction and adjacent to the fin structure,
a non-active electrode extending in the second direction while intersecting the fin structure, and
a blocking insulation film between the non-active electrode and the fin structure, the blocking insulation film being formed of a material different from that of the first semiconductor patterns; and

a plurality of contact plugs connected to the source/drain regions and the epitaxial region.

14. The semiconductor device as claimed in claim 13 , wherein:
the transistor further includes first gate spacers on both side surfaces of the gate electrode facing in the second direction, and
the non-active component further includes second gate spacers on both side surfaces of the non-active electrode facing in the second direction.

15. The semiconductor device as claimed in claim 14 , wherein the blocking insulation film is on a region of the fin structure located between the second gate spacers.

16. The semiconductor device as claimed in claim 14 , wherein:
the fin structure includes a plurality of fin structures arranged in the second direction, and
the epitaxial region is between fin structures of the plurality of fin structures.

17. The semiconductor device as claimed in claim 13 , wherein the epitaxial region includes epitaxial regions on both sides of the fin structure facing in the first direction with the fin structure interposed therebetween.

18. A semiconductor device, comprising:
a first transistor on a first conductive well of a substrate, the first transistor including:
first source/drain regions,
a plurality of first channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate while connecting the first source/drain regions, respectively,
a first gate electrode surrounding each of the plurality of first channel layers, and
a first gate insulator between the first gate electrode and the plurality of first channel layers;
a second transistor on a second conductive well of the substrate, the second transistor including:
second source/drain regions,
a plurality of second channel layers spaced apart from each other in the direction perpendicular to the upper surface of the substrate while connecting the second source/drain regions, respectively,
a second gate electrode surrounding each of the plurality of second channel layers, and
a second gate insulator between the second gate electrode and the plurality of second channel layers; and
a non-active component on the second conductive well of the substrate, the non-active component including:
a fin structure including a plurality of first semiconductor patterns alternately stacked with a plurality of second semiconductor patterns,
an epitaxial region adjacent to the fin structure,
a non-active electrode disposed to intersect the fin structure, and
a blocking insulation film between the non-active electrode and the fin structure, the blocking insulation film being formed of a material that is different from that of the first semiconductor patterns.

19. The semiconductor device as claimed in claim 18 , wherein the second transistor further includes an internal spacer between the second gate electrode and the second source/drain regions.

20. The semiconductor device as claimed in claim 18 , wherein the epitaxial region of the non-active component includes a semiconductor epitaxial portion that is the same as the first source/drain regions of the first transistor.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Woo Seok
• Song Seung Min
• Yang Jung Gil
• Bae Geum Jong
• Bae Dong Il

Classifications

• H01L29/41791

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L29/0642 Primary

  Electricity · mapped topic

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title