Dislocation stress memorization technique (DSMT) on epitaxial channel devices

Patent metadata

Field	Value
Publication number	US-9899517-B2
Application number	US-201615345814-A
Country	US
Kind code	B2
Filing date	Nov 8, 2016
Priority date	Apr 14, 2014
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to a channel region. In some embodiments, the transistor device has an epitaxial source region arranged within a substrate. An epitaxial drain region is arranged within the substrate and is separated from the epitaxial source region by a channel region. A first DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial source region to a location within the epitaxial source region. A second DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial drain region to a location within the epitaxial drain region.

First claim

What is claimed is:

1. A transistor device, comprising:
an epitaxial source region arranged within a substrate;
an epitaxial drain region arranged within the substrate and separated from the epitaxial source region by a channel region; and
first and second dislocation stress memorization (DSM) regions comprising stressed lattices configured to generate stress within the channel region, wherein the first DSM region extends from below the epitaxial source region to a first location within the epitaxial source region and the second DSM region extends from below the epitaxial drain region to a second location within the epitaxial drain region.

2. The transistor device of claim 1 , further comprising:
a gate structure arranged over the channel region, wherein the first DSM region is separated from the gate structure by the epitaxial source region and the second DSM region is separated from the gate structure by the epitaxial drain region.

3. The transistor device of claim 1 , wherein the epitaxial source region comprises a protrusion extending outward from an upper surface of the epitaxial source region.

4. The transistor device of claim 3 , wherein the protrusion extends outward to a location over a top surface of the substrate.

5. The transistor device of claim 1 , further comprising:
a recessed source contact located within a recess disposed along a top surface of the epitaxial source region, wherein the first DSM region extends from a location below the epitaxial source region to a lower surface of the recessed source contact.

6. The transistor device of claim 1 , wherein the first DSM region comprises a stacking defect.

7. The transistor device of claim 1 , wherein the first DSM region is arranged within and laterally offset from opposing sidewalls of the epitaxial source region.

8. The transistor device of claim 1 , wherein the first DSM region extends to a distance below the epitaxial source region that is greater than approximately 2 nm.

9. The transistor device of claim 1 , wherein the epitaxial source region and the epitaxial drain region comprise silicon phosphate.

10. The transistor device of claim 1 , wherein the first DSM region and the second DSM region comprise an n-type dopant species.

11. The transistor device of claim 10 , wherein the n-type dopant species comprises germanium.

12. The transistor device of claim 1 , wherein the epitaxial source region is substantially symmetric about an axis of symmetry vertically bisecting the epitaxial source region, and wherein the first DSM region is arranged along the axis of symmetry.

13. A transistor device, comprising:
an epitaxial source region separated from an epitaxial drain region by a channel region underlying a gate structure;
a first dislocation stress memorization (DSM) region comprising a first stressed lattice arranged within and laterally offset from opposing sidewalls of the epitaxial source region; and
a second DSM region comprising a second stressed lattice arranged within and laterally offset from opposing sidewalls of the epitaxial drain region.

14. The transistor device of claim 13 , wherein the first and second DSM regions respectively extend below bottom surfaces of the epitaxial source region and the epitaxial drain region.

15. The transistor device of claim 13 , wherein epitaxial source region is substantially symmetric about an axis of symmetry vertically bisecting the epitaxial source region, and wherein the first DSM region is arranged along the axis of symmetry.

16. The transistor device of claim 13 , wherein the gate structure comprises:
a gate electrode separated from the channel region by a gate dielectric layer; and
sidewall spacers arranged on opposing sides of the gate electrode.

17. The transistor device of claim 13 , wherein the epitaxial source region and the epitaxial drain region laterally extend below the gate structure.

18. The transistor device of claim 13 , wherein the first DSM region and the second DSM region comprise a re-crystallized amorphous material.

19. A transistor device, comprising:
an epitaxial source region separated from an epitaxial drain region by a channel region underlying a gate structure;
a first stacking defect arranged within and laterally offset from opposing sidewalls of the epitaxial source region; and
a second stacking defect arranged within and laterally offset from opposing sidewalls of the epitaxial drain region.

20. The transistor device of claim 19 , wherein the first stacking defect extends from within the epitaxial source region to below the epitaxial source region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Tsung Hsing
• Huang Shih Syuan
• Sheu Yi Ming
• Goto Ken Ichi

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/226

  at a temperature lower than room temperature · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01L29/66477

  Electricity · mapped topic