Semiconductor device having a cell separation pattern in contact with the bit line contact

Patent metadata

Field	Value
Publication number	US-12453082-B2
Application number	US-202318109442-A
Country	US
Kind code	B2
Filing date	Feb 14, 2023
Priority date	Jun 24, 2022
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A semiconductor device includes a cell active pattern including a first portion and a second portion that are spaced apart from each other; a gate structure between the first portion and the second portion of the cell active pattern; a bit-line contact on the first portion of the cell active pattern; a connection pattern on the second portion of the cell active pattern; and a cell separation pattern in contact with the bit-line contact and the connection pattern, wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact, an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a cell active pattern including a first portion and a second portion that are spaced apart from each other;
a gate structure between the first portion and the second portion of the cell active pattern;
a bit-line contact on the first portion of the cell active pattern;
a connection pattern on the second portion of the cell active pattern; and
a cell separation pattern in contact with the bit-line contact and the connection pattern,
wherein:
the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact,
an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and
a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.

2. The semiconductor device as claimed in claim 1 , wherein a lowermost portion of the bit-line contact is at a level higher than a level of a lowermost portion of the cell separation pattern.

3. The semiconductor device as claimed in claim 1 , wherein:
the upper portion of the second sidewall of the cell separation pattern is curved, and
the lower portion of the second sidewall of the cell separation pattern is flat.

4. The semiconductor device as claimed in claim 1 , wherein:
the gate structure extends in a first direction,
the first sidewall of the cell separation pattern is parallel to a second direction that intersects the first direction, and
the lower portion of the second sidewall of the cell separation pattern is parallel to a third direction that intersects the first direction and the second direction.

5. The semiconductor device as claimed in claim 1 , wherein:
the gate structure includes a gate dielectric layer, a gate electrode on the gate dielectric layer, and a gate capping layer on the gate electrode, and
the gate capping layer includes an intervention between the gate dielectric layer and the lower portion of the second sidewall of the cell separation pattern.

6. The semiconductor device as claimed in claim 5 , wherein a top surface of the intervention of the gate capping layer is in contact with the bit-line contact.

7. The semiconductor device as claimed in claim 5 , wherein the lower portion of the second sidewall of the cell separation pattern is in contact with a sidewall of the intervention of the gate capping layer.

8. The semiconductor device as claimed in claim 1 , further comprising a dielectric line on the gate structure,
wherein the first sidewall of the cell separation pattern is in contact with the dielectric line.

9. The semiconductor device as claimed in claim 1 , further comprising a dummy region and a dummy separation pattern over the dummy region,
wherein the dummy separation pattern includes:
a first sidewall parallel to the first sidewall of the cell separation pattern; and
a second sidewall parallel to the lower portion of the second sidewall of the cell separation pattern.

10. A semiconductor device, comprising:
a cell active pattern including a first portion and a second portion that are spaced apart from each other;
a gate structure between the first portion and the second portion of the cell active pattern;
a bit-line contact on the first portion of the cell active pattern;
a connection pattern on the second portion of the cell active pattern; and
a cell separation pattern in contact with the bit-line contact and the connection pattern,
wherein a lowermost portion of the bit-line contact is at a level higher than a level of a lowermost portion of the cell separation pattern.

11. The semiconductor device as claimed in claim 10 , wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact.

12. The semiconductor device as claimed in claim 11 , wherein:
the second sidewall of the cell separation pattern includes a first portion in contact with the bit-line contact and a second portion spaced apart from the bit-line contact,
an upper portion of the first portion of the second sidewall of the cell separation pattern is curved, and
a lower portion of the first portion of the second sidewall of the cell separation pattern is flat.

13. The semiconductor device as claimed in claim 12 , wherein the second portion of the second sidewall included in the cell separation pattern is coplanar with the lower portion of the first portion of the second sidewall included in the cell separation pattern.

14. The semiconductor device as claimed in claim 11 , wherein:
an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and
a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.

15. The semiconductor device as claimed in claim 14 , wherein:
the upper portion of the second sidewall of the cell separation pattern is curved, and
the lower portion of the second sidewall of the cell separation pattern is flat.

16. The semiconductor device as claimed in claim 11 , wherein:
the gate structure extends in a first direction,
the first sidewall of the cell separation pattern is parallel to a second direction that intersects the first direction, and
a lower portion of the second sidewall of the cell separation pattern is parallel to a third direction that intersects the first direction and the second direction.

17. The semiconductor device as claimed in claim 11 , further comprising a dielectric line on the gate structure,
wherein the first sidewall of the cell separation pattern is in contact with the dielectric line.

18. The semiconductor device as claimed in claim 10 , wherein an uppermost portion of the first portion of the cell active pattern is at a level higher than the level of the lowermost portion of the cell separation pattern.

19. A semiconductor device, comprising:
a substrate that includes a cell region, a dummy region, and a cell active pattern on the cell region, the cell active pattern including a first portion and a second portion that are spaced apart from each other;
a gate structure between the first portion and the second portion of the cell active pattern;
a bit-line contact on the first portion of the cell active pattern;
a connection pattern on the second portion of the cell active pattern;
a cell separation pattern over the cell region and in contact with the bit-line contact and the connection pattern; and
a dummy separation pattern over the dummy region and spaced apart from the bit-line contact,
wherein:
the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact,
the dummy separation pattern includes a first sidewall parallel to the first sidewall of the cell separation pattern and a second sidewall connected to the first sidewall of the dummy separation pattern,
the second sidewall of the cell separation pattern is curved, and
the second sidewall of the dummy separation pattern is flat.

20. The semiconductor device as claimed in claim 19 , further comprising a dummy line structure over the dummy region,
wherein the dummy separation pattern is closer than the cell separation pattern to the dummy line structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kiseok
• Kim Jongmin
• Kim Hyo-Sub
• Kim Hui-Jung
• Park Sohyun
• Ahn Junhyeok
• Yoon Chan-Sic
• Lee Myeong-Dong
• Jeong Woojin
• Choi Wooyoung

Classifications

• H10B12/485

  Bit line contacts · CPC title

• H10B12/053

  the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383) · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10B12/482 Primary

  Bit lines · CPC title