Semiconductor devices having expanded recess for bit line contact

Patent metadata

Field	Value
Publication number	US-9831172-B2
Application number	US-201514971402-A
Country	US
Kind code	B2
Filing date	Dec 16, 2015
Priority date	Dec 17, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region, and a third active region in a substrate, a recess region exposing an upper surface of the first active region and upper surfaces of the first and second device isolation regions, and active buffer patterns on the second and third active regions. The first active region is located between the second and third active regions, the first device isolation region is located between the first and second active regions, the second device isolation region is located between the first and third active regions. Upper sidewalls of the second and third active regions are exposed in the recess region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a first device isolation region and a second device isolation region defining a first active region, a second active region, and a third active region in the substrate, wherein the first active region is located between the second and third active regions, the first device isolation region is located between the first and second active regions, and the second device isolation region is located between the first and third active regions;
a recess region in the substrate on an upper surface of the first active region, upper surfaces of the first and second device isolation regions and upper sidewalls of the second and third active regions in the recess region;
active buffer patterns on the second and third active regions; and
wherein the recess region includes a flat floor that extends across the upper surface of the first active region and also extends across the upper surfaces of the first and second device isolation regions
such that the upper surface of the first active region and the upper surfaces of the first and second device isolation regions are coplanar.

2. The semiconductor device of claim 1 , further comprising:
a third device isolation region and a fourth device isolation region in the substrate,
wherein the second active region is located between the first and third device isolation regions, and the third active region is located between the second and fourth device isolation regions.

3. The semiconductor device of claim 2 , wherein an upper surface of the second active region is higher than the upper surface of the first device isolation region and lower than an upper surface of the third device isolation region, and
wherein an upper surface of the third active region is higher than the upper surface of the second device isolation region and lower than an upper surface of the fourth device isolation region.

4. The semiconductor device of claim 1 , wherein the active buffer patterns are formed on only the second and third active regions.

5. The semiconductor device of claim 2 , wherein the active buffer patterns comprise:
lower active buffer patterns on the second and third active regions; and
upper active buffer patterns on the lower active buffer patterns that are on the second and third active regions, and on the third and fourth device isolation regions.

6. The semiconductor device of claim 5 , wherein upper surfaces of the lower active buffer patterns and upper surfaces of the third and fourth device isolation regions are coplanar.

7. The semiconductor device of claim 2 , wherein an upper surface of the second active region is higher than the upper surface of the first device isolation region and coplanar with an upper surface of the third device isolation region, and
wherein an upper surface of the third active region is higher than the upper surface of the second device isolation region and coplanar with an upper surface of the fourth device isolation region.

8. The semiconductor device of claim 7 , wherein the active buffer patterns on the second the third active regions extend onto the third and fourth device isolation regions, respectively.

9. The semiconductor device of claim 2 , wherein an upper surface of the second active region is higher than upper surfaces of the first and third device isolation regions, and an upper surface of the third active region is higher than upper surfaces of the second and fourth device isolation regions.

10. The semiconductor device of claim 9 , further comprising:
contact pads between the second and third active regions and the active buffer patterns; and
device isolation buffer patterns on the respective third and fourth device isolation regions.

11. The semiconductor device of claim 10 , wherein upper surfaces of the active buffer patterns and upper surfaces of the device isolation buffer patterns are coplanar.

12. The semiconductor device of claim 10 , wherein the contact pads include upper contact pads on the upper surfaces of the second and third active regions, and side contact pads on the upper sidewalls of the second and third active regions exposed in the recess region.

13. A semiconductor device, comprising: a substrate;
a first device isolation region, a second device isolation region, a third device isolation region, and a fourth device isolation region defining a first active region, a second active region, a third active region, a fourth active region, and a fifth active region in the substrate, wherein the first active region is located between the second and third active regions, the second active region is located between the first and fourth active regions, the third active region is located between the first and fifth active regions, the first device isolation region is located between the first and second active regions, the second device isolation region is located between the first and third active regions, the third device isolation region is located between the second and fourth active regions, and the fourth device isolation region is located between the third and fifth active regions;
a recess region in the substrate on an upper surface of the first active region, upper surfaces of the first and second device isolation regions and upper sidewalls of the second and third active regions in the recess region; and
active buffer patterns on the second to fifth active regions; and
wherein the recess region includes a flat floor that extends across the upper surface of the first active region and also extends across the upper surfaces of the first and second device isolation regions such that the upper surface of the first active region and the upper surfaces of the first and second device isolation regions are coplanar.

14. The semiconductor device of claim 13 , wherein the active buffer patterns extend onto the third and fourth device isolation regions.

15. A semiconductor device, comprising: device isolation regions defining a plurality of adjacent active regions in a substrate, wherein each of the active regions has a first contact area at a center portion and a second contact area and a third contact area at both end portions;
a recess region on upper surfaces of the first contact areas of the active regions, upper surfaces of the device isolation regions located at both sides of the first contact areas and upper sidewalls of the second and third contact areas in the recess region;
buffer patterns on the second and third contact areas of the active regions: and
wherein the recess region includes a flat floor that extends across the upper surfaces of the first contact areas of the active regions and also extends across the upper surfaces of the device isolation regions located at both sides of the first contact areas such that the upper surfaces of the first contact areas of the active regions and the upper surfaces of the device isolation regions located at both sides of the first contact areas are coplanar.

16. The semiconductor device of claim 15 , further comprising:
bit line contact plugs on the first contact areas; and
bit line structures on the bit line contact plugs.

17. The semiconductor device of claim 16 , further comprising:
a spacer layer surrounding the bit line contact plugs and the bit line structures and filling the recess region; and
an interlayer insulating layer surrounding side surfaces of the spacer layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Daeik
• Park Jemin
• Han Sunghee
• Hwang Yoosang

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H01L23/5223 Primary

  Electricity · mapped topic

• H01L27/10855

  Electricity · mapped topic

• H01L27/10814

  Electricity · mapped topic